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xil_tour
Explorer
Explorer
454 Views
Registered: ‎06-14-2018

Simple VHDL code, can't simulate because of a syntax error, [HDL 9-806].

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Hi,

I modified a simple SPI code to make it even simpler (master only, one slave, 8 bit data, activated on CE impulse). It sends a fixed octet.

It seems to work on hardware, but I want to test it (yeah, i know it's the other way round but I can't simulate) extensively.

I marked both design and testbench as VHDL 2008.

Design:

-------------------------------------------------------------------------------
-- Title      : "SPI Master"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : spitest.vhdl
-- Author     : Tom Scott www.mispi_out_SSiontech.co.nz
-- Company    : Mispi_out_SSion Technologies        
-- Created    : 2007-02-05
-- Last update: 2007-05-10
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: Creates a simple SPI Master
-------------------------------------------------------------------------------
-- Copyright (c) 2007 Mispi_out_SSion Technologies
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2007-05-10  1.0      toms    Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------
entity spitest is
  generic (div : integer := 12500000);
  port (
    spi_in_RESET    : in  std_logic;
    spi_in_CLK      : in  std_logic;
    spi_out_SCLK     : out std_logic;
    spi_out_SS       : out std_logic;
    spi_out_MOSI     : out  std_logic;
    --spi_in_DataToTx : in std_logic_vector(15 downto 0);
    spi_in_CE  : in std_logic;
    
    LED_CE          : out std_logic;
    
    LED_SCLK        : out std_logic;
    LED_SS          : out std_logic;
    LED_MOSI        : out std_logic;
    LED_INDEX       : out std_logic_vector(3 downto 0)
  );
end spitest;

architecture a of spitest is
    type state_type is (idle, txBit, CheckFinished);
    signal state : state_type;
    signal spi_in_DataToTx : std_logic_vector(7 downto 0) := x"07";
    
begin

  process(spi_in_CLK, spi_in_RESET, spi_in_CE)
    variable index : integer := 7;
    variable dataLen : integer := 7; -- this must be set for the length of
    variable counter : integer range 0 to div-1; -- the data word to be txd
    
  begin
    if spi_in_RESET = '1' then
      spi_out_SCLK <= '1'; LED_SCLK <= '1';
      spi_out_SS <= '1'; LED_SS <= '1';
      spi_out_MOSI <= 'Z'; LED_MOSI <= '0';
      index := 7;
      dataLen := 7;
      counter := 0;
      
    else
      if(rising_edge(spi_in_CLK)) then
      
        LED_CE    <=  spi_in_CE ;
        
        if (counter = div-1) then
          counter := 0;
          
          case state is
            when idle =>
              spi_out_SCLK <= '0'; LED_SCLK <= '0';
              if(spi_in_CE = '1') then
                state <= txBit;
                spi_out_SS <= '0'; LED_SS<= '0'; 
              else
                state <= idle;
                spi_out_SS <= '1'; LED_SS <= '1';
                index := 7;
              end if;
      
            when txBit =>
              spi_out_MOSI <= spi_in_DataToTx(index); LED_MOSI <= spi_in_DataToTx(index);
              spi_out_SCLK <= '0'; LED_SCLK <= '0';
              state <= checkFinished;
              
            when checkFinished =>
              if(index = 0) then
                state <= idle;
                spi_out_SCLK <= '1'; LED_SCLK <= '1';
              else
                state <= txBit;
                index := index - 1;
                spi_out_SCLK <= '1'; LED_SCLK <= '1';
              end if;
          
            when others => null;
          end case;
          
        else
          counter := counter + 1;
        end if;
        
      end if;   
    end if;     
  
  end process; 
end a;

 

Testbench:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity spitest_tb is
end;

architecture bench of spitest_tb is

  component spitest
    generic (div : integer := 12500000);
    port (
      spi_in_RESET    : in  std_logic;
      spi_in_CLK      : in  std_logic;
      spi_out_SCLK     : out std_logic;
      spi_out_SS       : out std_logic;
      spi_out_MOSI     : out  std_logic;
      spi_in_CE  : in std_logic;
      LED_CE          : out std_logic;
      LED_SCLK        : out std_logic;
      LED_SS          : out std_logic;
      LED_MOSI        : out std_logic;
      LED_INDEX       : out std_logic_vector(3 downto 0)
    );
  end component;

  signal spi_in_RESET: std_logic;
  signal spi_in_CLK: std_logic;
  signal spi_out_SCLK: std_logic;
  signal spi_out_SS: std_logic;
  signal spi_out_MOSI: std_logic;
  signal spi_in_CE: std_logic;
  signal LED_CE: std_logic;
  signal LED_SCLK: std_logic;
  signal LED_SS: std_logic;
  signal LED_MOSI: std_logic;
  signal LED_INDEX: std_logic_vector(3 downto 0) ;

  constant clock_period: time := 10 ns;
  signal stop_the_clock: boolean;

begin

  -- Insert values for generic parameters !!
  uut: spitest generic ( div => 12500000 )
                  port map ( spi_in_RESET => spi_in_RESET,
                             spi_in_CLK   => spi_in_CLK,
                             spi_out_SCLK => spi_out_SCLK,
                             spi_out_SS   => spi_out_SS,
                             spi_out_MOSI => spi_out_MOSI,
                             spi_in_CE    => spi_in_CE,
                             LED_CE       => LED_CE,
                             LED_SCLK     => LED_SCLK,
                             LED_SS       => LED_SS,
                             LED_MOSI     => LED_MOSI,
                             LED_INDEX    => LED_INDEX );

  stimulus: process
  begin
  
    -- Put initialisation code here
    spi_in_RESET <= '1';
    wait for 50 ns;
    spi_in_RESET <= '0';
    wait for 50 ns;
    spi_in_CE <= '1';
    wait for 50 ns;
    spi_in_CE <= '0';
    
    -- Put test bench stimulus code here

    stop_the_clock <= true;
    wait;
  end process;

  clocking: process
  begin
    while not stop_the_clock loop
      spi_in_CLK <= '0', '1' after clock_period / 2;
      wait for clock_period;
    end loop;
    wait;
  end process;

end;

Any remark about the syntax is welcome.

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1 Solution

Accepted Solutions
shantmoses
Contributor
Contributor
442 Views
Registered: ‎07-01-2008

Hi,

 

Just visually inspecting your code I noticed the missing "map" keyword after generic.

uut: spitest generic map ( div => 12500000 )

 

Cheers

 

View solution in original post

4 Replies
shantmoses
Contributor
Contributor
443 Views
Registered: ‎07-01-2008

Hi,

 

Just visually inspecting your code I noticed the missing "map" keyword after generic.

uut: spitest generic map ( div => 12500000 )

 

Cheers

 

View solution in original post

xil_tour
Explorer
Explorer
430 Views
Registered: ‎06-14-2018

Thanks I've made the correction, silly me.

Now I got another error:

[VRFC 10-3146] binding entity 'spitest' does not have generic 'div' ["/mnt/opt/vivado/segment_spi/segment_spi.srcs/sim_1/new/spitest_tb.vhd":11]

 

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xil_tour
Explorer
Explorer
413 Views
Registered: ‎06-14-2018

Nevermind the VRFC-3146 error, the behavioral simulation seems to work, I'll dig that now.

 

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xil_tour
Explorer
Explorer
398 Views
Registered: ‎06-14-2018

As expected, the design is ugly, don't use that

Thanks shantmoses.

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