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Adventurer
Adventurer
286 Views
Registered: ‎08-04-2018

Simulating VN VP in XADC

Hello all, 

 

I am trying to write a test bench for giving values to VP and VN and see the simulation of the XADC, but how? xili.PNG

 

I have generated the top module for this and I instantiate and want to give some values  to VN and VP and see how the logic works, but the type is STD_LOGIC for VN and VP pins.. how to provide data? So i can see the logic working ? can any one suggest any ideas?

 

 

Thanks in Advance.

 

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Xilinx Employee
Xilinx Employee
274 Views
Registered: ‎11-30-2007

Re: Simulating VN VP in XADC

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