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Adventurer
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Registered: ‎01-18-2019

Simulation Sets - how to rename them, move files, include DUT submodules

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Hi All,

Once you grasp the essence of a feature or tool they are fairly simple but it takes quite an effort to get there.

Right now I am wrestling with Simulation Sets in Vivado 2018.3.

 

Question 1:        Can you rename a Simulation Set? How?

Question 2:        Can you move files over from one Simulation Set to another? How?

Question 3:        Does it make sense not to allow an RTL file to be used in Simulation (but in Synth./Impl. only)?  What would that be?

Question 4:        It seems I either have all the DUT source files in a new Simulation Set (default) included, or I need to manually include the DUT module source file and its submodule files I want to simulate with the testbench. I wonder if I could select an option where the testbench file itself determines which submodule RTL sources it needs. Possible?

Thank you.

Miklos  

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Xilinx Employee
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Registered: ‎07-16-2008

回复: Simulation Sets - how to rename them, move files, include DUT submodules

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Yes, I think your understanding is right.

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Xilinx Employee
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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1. There's a default simset called 'sim_1' when you create a project. You can create a new simset with a custom name.

2. You can edit individual simulation set to remove or add files.

3. That depends on your need. You might define a simulation set to provide a test bench for a specific module. Other sources may be used in synthesis/implementation only.

4. By default, the same sources as in the design sources top level will be included in the simset. You may want to add a test bench based on a submodule and set the tb as top in simset. I think this will allow corresponding pieces of hierarchy to be displayed under the top.

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Adventurer
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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I appreciate your intention and effort trying to help, but your reply did not help much. :(

>>Question 3: Does it make sense not to allow an RTL file to be used in Simulation (but in Synth./Impl. only)? What would that be?
> 3. That depends on your need. You might define a simulation set to provide a test bench for a specific module. Other sources may be used in synthesis/implementation only.
The "Used in..." option offers to disallow an RTL file in simulation.
But does anyone dare to design anything without ever simulating it before synthesis and implementation?
Does anyone let his/her RTL design file go into production without ever putting it to the test?
If you can mark testbench files as 'files for simulation only', but not for synthesis, that makes sense.
But to mark a DUT RTL files as 'files for synthesis/implmentation only', but not for simulation, that makes no sense to me.
And I wonder what conception I am missing here.


>>Question 4: It seems I either have all the DUT source files in a new Simulation Set (default) included, or I need to manually include the DUT module source file and its submodule files I want to simulate with the testbench. I wonder if I could select an option where the testbench file itself determines which submodule RTL sources it needs. Possible?

>4. By default, the same sources as in the design sources top level will be included in the simset. You may want to add a test bench based on a submodule and set the tb as top in simset. I think this will allow corresponding pieces of hierarchy to be displayed under the top.

Yes, this is what I have been doing.
But in that case there is no need for simsets at all.
I was trying to find out in what way are simsets better than this solution. 

From what I have found out about simsets so far, it seems to me that they are useless.

Miklos

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Xilinx Employee
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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@mbence76  已写:

I appreciate your intention and effort trying to help, but your reply did not help much. :(

>>Question 3: Does it make sense not to allow an RTL file to be used in Simulation (but in Synth./Impl. only)? What would that be?

But to mark a DUT RTL files as 'files for synthesis/implmentation only', but not for simulation, that makes no sense to me.
And I wonder what conception I am missing here.

 


It looks that you're answering your own questions. You have the option to enable/disable the used in sources. Every file has the property. That's it.

I also agree that you don't want to modify this for DUT sources. Typically you can check simulation only for test bench file. 

 

As for the simulation set, it allows you to create and manage multiple simulation configurations, something like design runs. You can try out these configurations and preserve the simulation results. Switching top level in a single simset gives you the single current simulation result.

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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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>It looks that you're answering your own questions. You have the option to enable/disable the used in sources. Every file has the property. That's it.

If every kind of file is to be used for simulation, then why is it optional? If there were options like functional_sim / post-synth_functional_sim / timing_sim, then it would make a little more sense to make it selectable, but in general "simulation" is needed for everything.  Anyway, I can live with that.

The other point: Simulation Sets.

>As for the simulation set, it allows you to create and manage multiple simulation configurations, something like design runs. You can try out these configurations and preserve the simulation results. Switching top level in a single simset gives you the single current simulation result.

You are right, I forgot about that, it makes sense, good point, thank you.

However, something is just wierd here.
1) Once you added a file to a simset, you cannot remove it, unless you remove it from the whole project. That is not normal.
2) I selected RTL design files and accidentally clicked on 'Move to simulation sources' and they disapperad from my Design Sources list and apperead twice under the same simset. I just cannot move them back. I tried to remove them from the project and re-add them to my Design Sources list, but they re-appeared in my simset list again.  This is crazy. Is this a bug? Please see the image. Untill now DUT files used to appear only as submodules of the testbench files.

simset_file_duplicates.PNG

 

Thank you for your time.

Miklos

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Xilinx Employee
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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I had a try at my end. Once the file is moved to simulation sources, I can see 'Move to Design Sources' available in the right-click menu. It works at my end.

move_file.jpg

The equivalent Tcl command is:

move_files [get_files <path>/filename]

 

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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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By now all I want to know is how to remove an unwanted DUT RTL file from a simset.

If you select an unwanted DUT RTL file in a simset, then these are you options:

  1. remove from project       - not good
  2. disable file                      - not good
  3. rewoke the usedin property for simulation    - not good, I do want to simulate it in another simset
  4. replace file                      - not good
  5. move it to simulation sources - not good, it makes it disappear from the Design Sources folder.

The "move to design sources" option comes up only if the file is a testbench (used in 'simulation' only).

What you can do is add a new dummy file to make the include checkbox live (not gray), uncheck it, and click Finish.
This will remove all the DUT files. All of them. I want to get rid of the unwanted one (and in one simset only).

If you add DUT RTL files manually, they do not necessarily form a hierarchy. Sometimes yes, sometimes no even if syntax is OK.

Why can't  I say add submod1.sv and have everything under it included automatically?

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Xilinx Employee
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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@mbence76  已写:

The "move to design sources" option comes up only if the file is a testbench (used in 'simulation' only).

 


This is not true in my test. As shown in the figure in my previous answer, it's available for a DUT RTL source file, which is not used in simulation only.

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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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I have made a sample project, it has no SystemVerilog interfaces, no typedefs, to make things easier.

1 top module.

2 submodules.

2 simsets.

Under certain conditions you can move DUT files back to Design Sources, but I cannot figure out what they are.

All three DUT files (top, sub1, sub2) have all three usedin properties checked in.

Please see these images.


Image 1: here it is as it should be, but I would not want to remove that file, since it is the only DUT file in the simset.

MoveToDesSources.png


Image 2: Here I have the whole project in the simset but I want to test submod2 only.

I do not know how to remove TOP_module and its submodules. (I want submod2 only once, under tb_2.)

MoveToSimSources_1.png


Image 3:  Even if I wanted to get rid of submod_2  in sim_2, I would not know how to do it.

MoveToSimSources_2.png

Apperently I missing the concept here.

 

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Xilinx Employee
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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If you want to test submod2 only, please uncheck "Include all design sources for simulation" when you add files (tb_2.sv & submod_2.sv) to the newly created simset.

Here's an illustration.

add_file_simset.jpg

 

By default, it copies all design source files from the sources_1 fileset into the simulation fileset.

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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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>By default, it copies all design source files from the sources_1 fileset into the simulation fileset.

I think now I have understood what one misconception was in my head (there might be some more.. ).

I was thinking that if you check the checkbox to include something then it will include those files and that is it.

But in reality, this checkbox is more like setting a property of the simset:  should it contain the DUT files or not.

"Not to include the DUT files" actually means to remove them even if they are already there

and "to include the DUT files" means you cannot remove them, unless you re-set this property of the simset (uncheck the box).

You can remove only the DUT files that you added manually.

You cannot remove DUT files that were included when simset was created. You must add a dummy DUT file to un-gray the checkbox and to uncheck it.

I was trying to create a simset without including anything and I added the submodule and the testbench manually, but my submodule was missing its own submodules (the BRAM files). I added the .xci file but it did not work hierarchy was still incomplete. Is it safe to say that the only time you need to check the include checkbox is when you want to simulate the whole design with the topmodule at the top? Otherwise one had better add the submodules manually. Am I right about this or wrong?

Thank you again for your time and patience.

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Xilinx Employee
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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Yes, I think your understanding is right.

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Adventurer
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回复: Simulation Sets - how to rename them, move files, include DUT submodules

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Well, then I see a tool improvement potential here:

how about deleteing this include checkbox altogether?

What the Vivado could do in return is that when you add a DUT file (say an RTL file), it could automatically include all the hierarchy beneath it with everything it needs to be operational.  (It would make little sense to include a submodul DUT RTL on its own. After all the goal is to simulate a subset of a bigger system.)

Just an idea. 

Anyway, thank you for you patience, Graces.

Miklos