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Simulation: behavioral, structural, functional, timing

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In Vivado and in ug900, I see the words (behavioral, structural, functional, timing) used to describe types of simulation. 

 

Can someone please explain the characteristics for each of these simulation types?

 

Also, specifically what prevents Vivado from doing post-implementation-timing simulation for a VHDL project?

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Xilinx Employee
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回复: Simulation: behavioral, structural, functional, timing

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Hi Mark,

Sorry for the delay in response. I must have missed your reply.

I managed to run timing simulation successfully by following these steps.

1. Set "pulse_stretch" as top level

2. Re-run implementation

3. Open Simulation Settings, go to Advanced tab and uncheck "Enable Incremental Compilation".

4. Launch post-implementation timing simulation

 

The problem with the previous setting is that the auto-generated timing simulation netlist is based on design top, while your UUT is "pulse_stretch". This leads to "pulse_stretch.vhd" being compiled and no simprims_ver components were loaded.

Step 3 is to cleanup the previously generated database.

Please have a try and let me know if it works for you.

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Xilinx Employee
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回复: Simulation: behavioral, structural, functional, timing

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As documented in UG900, the behavioral simulation is performed at RTL-level. It is typically performed to verify code syntax, and to confirm that the code is functioning as intended. In this step, the design is primarily described in RTL and
not architecture-specific unless the design contains an instantiated device library component.

 

Functional and timing simulations are performed post-synthesis or post-implementation. After synthesis or implementation, RTL is transformed to structural netlist, in which the lowest level of hierarchy consists of primitives and macro primitives. 

 

Take the following simple RTL that describes register behavior for example,

always @(posedge <clock>) begin
<reg> <= <signal>;
end

 

In behavioral simulation, the simulation model is the RTL code. After synthesis or implementation, you'll get a netlist that is expanded to FDRE primitive, which is the structural model.

Both functional and timing simulations are based on the structral model exported from synthesized or implemented design. For timing simulation, SDF is also needed to annotate timing information.

 

There's no VHDL version of the SIMPRIM library, so timing simulation is supported in Verilog only. This has been the case since Vivado launch.

 

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回复: Simulation: behavioral, structural, functional, timing

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Thank you @graces !

 

It is a problem with the English language that there are so many words with the same meaning. 

 

It seems to me that Vivado logic simulation has only two levels of classification:

 

(Level-1) When (in the flow) it is run:

  • RTL
  • Post-synthesis
  • Post-implementation

 

(Level-2) What modelling detail is used:

  • Ideal models (components behave ideally and operate with zero delay, wires/routing has zero delay)
  • Actual models (eg. using SPICE-like models that fully describe the time/delay behavior of components/routes)

 

Since routing and actual component information only becomes available after implementation, then the Level-2 distinction need only be made for post-implementation simulation.

 

So, Vivado logic simulation can be classified as follows:

            RTL (Ideal)

            Post-Synthesis (Ideal)

            Post-Implementation Ideal

            Post-Implementation Actual

 

Are your saying there is a fifth classification called "Post-Synthesis (Actual)"?  If so, can you describe how it is possible to use actual models at this stage in the flow?

 

Thanks,

Mark

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Xilinx Employee
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回复: Simulation: behavioral, structural, functional, timing

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I would say 'Post-Synthesis (Estimate)'.

Although it is not typical, you can perform timing simulation with estimated timing numbers at this simulation point.

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回复: Simulation: behavioral, structural, functional, timing

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Grace – again 謝謝 !

 

Synthesis is used to create a netlist from HDL (eg. VHDL or Verilog).  After the netlist is created, I understand that the Vivado flow moves forward with no memory of whether the netlist came from VHDL or Verilog.

 

I also understand(?) that post-synthesis simulation and post-implementation simulation use the netlist and that the SIMPRIM library is used to model netlist parts.  So, if these simulations start with a netlist that has no memory of the HDL, then why is post-implementation-timing simulation restricted to Verilog HDL?

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回复: Simulation: behavioral, structural, functional, timing

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The generated simulation netlist from original RTL is in the form of either VHDL or Verilog. By saying "timing simulation is supported in Verilog only", the Verilog refers to the post-synth/post_impl simulation netlist language. You can have a pure VHDL RTL design but write out a Verilog simulation netlist (write_verilog) from synthesized or implemented design. That netlist still allows you to perform timing simulation.

 

Verilog SIMPRIMS_VER uses the same source as UNISIM with the addition of specify blocks for timing annotation.

e.g. You can see something like this in Verilog UNISIM library components.

specify
(C => Q) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge C &&& CE, 0:0:0, notifier);
$period (posedge C &&& CE, 0:0:0, notifier);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);

 

This is not seen in their VHDL UNISIM counterparts. There's no SIMPRIM library for VHDL and therefore VHDL (netlist) timing simulation is not supported.

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回复: Simulation: behavioral, structural, functional, timing

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Thank you for Grace-iously correcting my misunderstanding.

 

You can have a pure VHDL RTL design but write out a Verilog simulation netlist (write_verilog) from synthesized or implemented design.

This is very good news!  Yes, I have a pure VHDL RTL design (ie. both the module to be simulated and my testbench are written in VHDL).

 

I am using Vivado in project mode.  In the Simulation settings, I can simply change the “Simulator Language” from VHDL to Verilog and get post-implementation-timing simulation to run with receiving Vivado error messages.  I can see in the Tcl Console that write_verilog has been automatically used by Vivado.

 

However, post-implementation-timing simulation looks exactly the same as post-implementation-functional simulation. That is, signals are changing exactly on the clock edges in both simulations (no real-circuit delays are evident).  

 

What must I do to make post-implementation-timing simulation show me the real-circuit delays?

 

PS.  I see the following warning in the Tcl Console (does this help us solve the problem?):

WARNING: Simulation object /tb_pulse_stretch/END_SIM was not traceable in the design for the following reason: Vivado Simulator does not yet support tracing of VHDL variables.

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Xilinx Employee
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回复: Simulation: behavioral, structural, functional, timing

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Did you see "write_sdf" as well? Was the generated SDF backannotated successfully?

Please share your elaborate.log for a look.

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回复: Simulation: behavioral, structural, functional, timing

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Did you see "write_sdf" as well?   Yes

 

Was the generated SDF backannotated successfully?  uhmm - I don't know.   Please see the attached text file, Tcl_Console.txt, which contains contents of the Vivado Tcl Console during my attempt to run post-implementation-timing simulation.

 

Please share your elaborate.log for a look.  It is attached.

 

 

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回复: Simulation: behavioral, structural, functional, timing

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It looks SDF annotation didn't happen. Otherwise you would see something like this in elaboration.

INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "tb_wave_gen_time_impl.sdf", for root module "tb_wave_gen/wave_gen_i0".
INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "tb_wave_gen_time_impl.sdf", for root module "tb_wave_gen/wave_gen_i0".

 

I do see write_verilog and write_sdf. From the 'compile' step, both the generated Verilog simulation netlist and VHDL file "pulse_stretch.vhd" are compiled. Is this "pulse_stretch.vhd" the top level testbench?

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回复: Simulation: behavioral, structural, functional, timing

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Thanks Grace!

 

I also do not see the INFO lines about SDF annotation.

 

I do see the following INFO line saying that a SDF file was generated:

INFO: [SIM-utils-37] SDF generated:C:/Vivado_projects/IO_testing1/IO_testing1.sim/sim_1/impl/timing/xsim/tb_pulse_stretch_time_impl.sdf

 

The VHDL testbench is called tb_pulse_stretch.vhd.

 

The VHDL component that is instantiated and tested in the testbench is called pulse_stretch.vhd.

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回复: Simulation: behavioral, structural, functional, timing

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Hi Grace,

 

In Vivado project-mode, post-implementation-timing simulation is still looking like post-implementation-functional simulation (ie. post-implementation-timing simulation is not showing any delays).  As I mentioned before, Vivado is not throwing any error messages.

 

As you noted, “It looks SDF annotation didn't happen”.

 

In simulation settings, I am specifying SDF annotation as shown below:

sim_setting.jpg

 

 

I am using Vivado Webpack v2017.3.1.  Is Webpack Vivado able to run post-implementation-timing simulation?

 

Any other ideas why post-implementation-timing simulation is not working for me?

 

Thanks,

Mark

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Xilinx Employee
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回复: Simulation: behavioral, structural, functional, timing

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I suspect this is a tool issue. It's expected that the post-impl timing simulation only loads the test bench, the verilog netlist as well as glbl. If the VHDL design unit is loaded too, something is messed up here.

Can you give it a try in the latest 2018.2?

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回复: Simulation: behavioral, structural, functional, timing

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Grace - many thanks for continued to struggle with me on this issue!

 

As you suggested, I tried Vivado v2018.2 and found that post-impl timing simulation looks the same as with Vivado v2017.3 - and still does not seem to work properly.

 

Attached is the elaborate.log and Tcl Console output from my attempt to run post-impl timing simulation with Vivado v2018.2.

 

-again thanks,

Mark

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回复: Simulation: behavioral, structural, functional, timing

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What do the .prj files in the simulation directory look like?

Can you share the test case?

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回复: Simulation: behavioral, structural, functional, timing

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Hi Grace,

 

Attached is an archive of my Vivado v2018.2 project called IO_testing1. It is a simple project that implements the following circuit.

PS1_schematic.jpg

 

Input, CLR1, is an asynchronous clear for register, REG1.  So, when CLR1 goes low then the output of REG1 (and output, OUT1) should go high shortly after the next rising edge of CLK1.   The “post-impl timing simulation” for this circuit is shown below and uses the testbench called tb_pulse_stretch.vhd.

PS_simul.jpg

 

Circuit delays should cause OUT1 to go high shortly after CLK1 goes high at 60ns. However, OUT1 and CLK1 go high simultaneously – as they do in “behavioral simulation”.

 

Again, thanks for continuing the struggle with me.

Mark

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回复: Simulation: behavioral, structural, functional, timing

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Hi Mark,

Sorry for the delay in response. I must have missed your reply.

I managed to run timing simulation successfully by following these steps.

1. Set "pulse_stretch" as top level

2. Re-run implementation

3. Open Simulation Settings, go to Advanced tab and uncheck "Enable Incremental Compilation".

4. Launch post-implementation timing simulation

 

The problem with the previous setting is that the auto-generated timing simulation netlist is based on design top, while your UUT is "pulse_stretch". This leads to "pulse_stretch.vhd" being compiled and no simprims_ver components were loaded.

Step 3 is to cleanup the previously generated database.

Please have a try and let me know if it works for you.

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回复: Simulation: behavioral, structural, functional, timing

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Hi Grace,

You are the master! 

Things now seem to be working for me.

From what I’ve seen on the Forum, you are one of very few people who know how to make Post-Implementation Timing Simulation (PITS) work.

I’m sorry to “look a gift-horse in the mouth”, but your solution is:

  • not consistent with the way we run other types of simulation in Vivado
  • not intuitive
  • kinda messy (I get 7 critical warnings for things being unrecognized in constraints file)

I hope you will put in a change order so that running PITS in future versions of Vivado is as easy as running the other types of simulation (eg. Behavioral Simulation).

-many, many thanks!
Mark

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回复: Simulation: behavioral, structural, functional, timing

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Hi Mark,

Thank you for the suggestions to make Vivado more user friendly. Let me explain a bit further.

When you click "Post-Implementation Timing Simulation", there're some underlying jobs that the tool will perform before launching simulation. It opens implemented design and writes out post-impl timing simulation netlist (write_verilog) and sdf (write_sdf). These files are then used for the timing simulation, along with the testbench and glbl.

The flow is by design. So you see the netlist is produced based on the current design. When you set a different module as top, it's out of sync.

I think the critical warnings are caused by changing top level. You may need to replace a constraint file that is applicable to the design under test.

 

Having said that, I agree the step to disable incremental compilation is not intuitive to user. I'll provide the feedback to Xsim team and get it addressed/improved.

Thanks,

Grace

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回复: Simulation: behavioral, structural, functional, timing

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Thank you, Grace!

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