11-05-2015 10:44 AM - edited 11-05-2015 10:55 AM
I used win7 64bit + vivado 2015.2
The behavorial functional simulation is totally fine. but the post-synthesis simulation failed.
The error message shows:
[USF-XSim 62] 'compile' step failed with error(s) while executing '****/**_project.sim/sim_1/synth/timing/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.
11-05-2015 12:48 PM
Please check the Tcl console if you are getting any error or warning message.
11-05-2015 01:27 PM - edited 11-05-2015 04:01 PM
Thx for your reply.
Hereby the msg in console:
Starting static elaboration
ERROR: [VRFC 10-2063] Module <FIFO_DMA_Out_4TestBench> not found while processing module instance <DMA_out_data_FIFO> [c:**/src/Simulation_Files/TB_data_mover_bridge.v:916]
WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 16 for port s00_axi_wdata [c:/**/src/Simulation_Files/TB_data_mover_bridge.v:599]
WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 2 for port s00_axi_wstrb [c:/**/src/Simulation_Files/TB_data_mover_bridge.v:600]
WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 16 for port s00_axi_rdata [c:/**/src/Simulation_Files/TB_data_mover_bridge.v:610]
WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port o_LED_indicator_channel_status [c:/**/src/Simulation_Files/TB_data_mover_bridge.v:709]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-99] Step results log file:'C:/DevGIT/DNA2_FGPA/DNA2_ZYNQ.tmp/data_mover_bridge_v1_35_14_project/Data_Mover_Bridge_v1_35_14_project.sim/sim_1/synth/timing/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/**/Data_Mover_Bridge_v1_35_14_project.sim/sim_1/synth/timing/elaborate.log' file for more information.
launch_simulation: Time (s):
It seems the issue is related with FIFO_DMA_Out_4TestBench FIFO ip. Actually this ip was only used in my simulation. The behavorial simulation worked with this IP in the project. Somehow it doesn't work now for post-synthysis simulation.
11-05-2015 07:58 PM
Please check the AR http://www.xilinx.com/support/answers/56492.html
11-06-2015 04:25 PM - edited 11-06-2015 04:25 PM
No, it doesn't work.
I followed the instruction as follow to install the patch:
METHOD 2: Overwriting files in existing Xilinx install area
a. Original files in the respective directories should be moved or
renamed before copying the archived files to these locations.
b. Extract the critical file(s) contents of the ".zip" archive to the
Vivado 2013.2 directory that you are patching
c. Run Vivado software tools from the original install location.
After the patch was installed, I tried to restart vivado. Then it shows this error msg (see the picture attached.)
I guess it's fit for vivado2015.2.
06-30-2017 03:49 PM
This seems to be a Windows only issue, but I am seeing this on a a Vivado 2017.1 installation on Fedora 7.
I am running post route timing simulations for a Virtex 7 Ultrascale xcvu440-flgb2377-1-i device.
06-30-2017 03:51 PM