11-12-2018 06:19 AM
I’m trying to run a simulation of an entity written in VHDL which contains a Xilinx IP « Multiplier ».
When launching the simulation the elaboration always fails with the log file attached.
We are using Vivado 2018.2.
I tried lots of different settings and searched on the Xilinx website without success.
Could you help me and let me know what is missing?
Attached is a simple project (test_mac) that uses our Core (SignedIntegerMAC), which is generated by Vivado.
Thanks for your help.
11-12-2018 09:17 PM
I tried to open the project, re-add the IP (as the previous association looks broken) and regenerate the IP.
After that, I can successfully launch behavioral simulation.
Would you please try to open Simulation Settings, go to Advanced tab and uncheck “Enable Incremental Compilation"?
11-12-2018 11:58 PM
Thanks for your answer, however unchecking "Enable incremental compilation" does not help. I still have the same error.
I tried to delete the xsim folder but still the same behavior. I also regenerated the IP but it did not change anything.
11-13-2018 02:23 AM
When I open the project that you supplied I get an error that the .xci file can not be found as it is being searched for on the w: drive.
You can see that it is missing in the following screen shot.
I then added the .xci file back in using Add Sources and pointing to the location of the file.
It now contains a working link so I right clicked on the IP and choose Generate Output Products.
The tools said that the products were up to date and didn't need regenerating, so I ran simulation.
Let me know if this helps.
11-13-2018 02:35 AM
On my computer the IP is located on drive W: so this is normal that on your computer you have to relocate the source.
I tried to remove the XCI file from my project source, then add it again, then generate output product (Vivado says the output is up-to-date).
When launching the simulation I still get the same error during elaboration.
I tried to move the source of the IP (the XCI file) to another place on my hard-drive. Same result.
11-13-2018 02:51 AM
Can you try the following before opening the project, delete the test_mac.sim directory and then open the project.
In the tcl console type reset_project to clear out the design runs.
Then try running the simulation again.
If this does not work, then as a test try creating a new project using only the Top,.vhd and SignedIntegerMAC.xci file.
11-13-2018 03:53 AM
I tried your ideas but nothing works, still the same errors during elaboration.
The sample project I sent you was already something built from scratch for this support case, but I created yet another project with only the top.vhd and XCI added and still get the same errors.
Any other ideas?
11-13-2018 11:07 PM - edited 11-13-2018 11:22 PM
The error messages are complaining about specific pre-compiled IP libraries.
If you keep receiving the exact same error as in the previous log, can you please check to see whether the pre-compiled files exist in the following paths?
Where $XILINX_VIVADO points to the Vivado install directory.
BTW, are you using 2018.2 or 2018.2.2? For 2018.2.2, there's a known issue that some pre-compiled IPs are missing from the install directory.
11-14-2018 09:56 PM
I checked and all folders are present:
D:\Xilinx\Vivado\2018.2\data\xsim\ip\xbip_pipe_v3_0_5 with 3 files (RLX, VDBL, VDBX)
D:\Xilinx\Vivado\2018.2\data\xsim\ip\xbip_multadd_v3_0_12 with 3 files (RLX, VDBL, VDBX)
I am using 2018.2, on Win7 x64
Which version were you using when you say that the project I sent was working at your end?
11-14-2018 10:46 PM
I tried in the same version as you, 2018.2.
Attached is the archive of the project that runs at my end. You may give it a try too.
11-14-2018 11:45 PM
If you download the install image from the website, I'd suggest that you verify the MD5 checksum.
If matched, try to re-install 2018.2.
11-15-2018 02:16 AM
I asked a colleague to try on his computer, with the same version of Vivado 2018.2 and he is able to simulate the sample project.
I compared the whole Vivado folder from his computer versus the one on my computer but they are identical.
Then i did uninstall Vivado from my computer, then re-install it with a fresh download (WebInstaller), reboot the computer. And still the same problem I cannot run the simulation.
I'm running out of ideas, what do there error messages mean, could you check in Vivado's source code to see what event could trigger these VRFC 10-147 and VRFC 10-213? I'm happy to run a debug version of Vivado if needed to help you track this bug.
11-15-2018 06:31 PM
Is it project specific on your machine?
For any other project that involves these IPs, do you see the same error?
11-15-2018 11:14 PM
I do have the same issue with other projects using the same IP.
I did create a new "Multiply Adder" IP, with different name and I have also the same behavior when launching the elaboration of the simulation.
If I launch a simulation using other Xilinx IP, like a float adder or float multiplier, it is working fine.
11-27-2018 02:44 AM
If you build the project on a local drive e.g. c: with the IP contained within and not referenced on a network drive do you see the same issue?
Did you get a chance to try the version of the project that either Grace or myself provided?
In an email it was mentioned that you have found a workaround, but that it is not ideal.
What are you doing differently that allows the simulation?
Please use the @amaccre in your reply otherwise we are not notified of the response and it is easy to miss replies
11-27-2018 07:57 AM
Thanks for coming back to me.
I'm not using a network drive, only a local drive, with a substed folder on W: (i.e. subst w: D:\temp)
I've tried the project version provided by @graces, both on the substed drive as well as directly on a local drive with the same result.
To be able to simulate I use the following workaround:
- Comment the instantiation of the Multiplier IP
- Uncomment the VHDL simulation code:
constant C_MAC_MULTIPLIER_LATENCY: integer := 7;
constant C_MAC_ADDER_LATENCY: integer := 3;
-- used for simulation SignedIntegerMAC_instance: process(LiveClk) type T_DelayLine is array(natural range <>) of signed(C_MAC_OUTPUT_BIT_RESOLUTION - 1 downto 0); variable mult_delay: T_DelayLine(0 to C_MAC_MULTIPLIER_LATENCY - C_MAC_ADDER_LATENCY - 1) := (others => (others => '0')); variable add_delay: T_DelayLine(0 to C_MAC_ADDER_LATENCY-2) := (others => (others => '0')); begin if rising_edge(LiveClk) then mac_result <= std_logic_vector(add_delay(add_delay'high)); add_delay := (mult_delay(mult_delay'high) + signed(operand_C)) & add_delay(0 to add_delay'high - 1); mult_delay := (signed(operand_A_sxt) * signed(operand_B)) & mult_delay(0 to mult_delay'high - 1); end if; end process;
Attached is the complete VHDL file including the Multiplier simulator.
This just give the same result than the IP with the same latency without the issues encountered while loading the IP.
11-27-2018 06:10 PM
Do you see the error if you run the project in the local drive rather than the mapped drive created by subst?
11-28-2018 03:36 AM
I cannot replicate the issue that you are seeing. I have set up Vivado to run from a network drive and have used the subst to match the drive letters that are in the project that you provided in the first post.
Could you run the simulation of this project so that it fails on your system and then zip up the test_mac.sim directory?
This will provide the scripts generated to run the simulation along with the log files that show the results.
I can then compare this with the results that I am seeing.
11-28-2018 05:42 AM
11-28-2018 08:34 AM
Thanks for the files, I compared your elaborate.log file to the version that I have locally and the only difference other than the file paths was the inclusion of the --incr option in my version of the project.. This is the switch for Enable incremental compilation in the Simulation Settings Avanced tab.
Unfortunately changing this setting still didn't replicate the issue.
The only other option that I can think of is to create a D: drive and install Vivado there to see if it makes a difference.
I will let you know the results once I have run them.