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pulsar
Explorer
Explorer
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Registered: ‎04-16-2015

Simulation of internal signals

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Hello all,
I want to do Post Implementattion Timing Simulation
for signals in top entity and for internal signals.
I look internal signals of interest in the Netlist/Nets
after "Open Implemented Design".
But after Post Implementattion Timing Simulation
I have no access to Netlist/Nets.

How do add internal signals to the simulation wave window ?

Thank you,

Best regards,
Viktor.
P.S. I worked in Vivado2017.3

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

That all makes sence.

Top level signals, that basically connect to IO pins, 

    can not be optimised away, unless they are not used, so you will always see them.

Pre P&R, then the simulator is workgin on your design as is,

    no optimisation, no duplication , so all signals are there.

Post P&R / synthesis, there is optimisation

    thus internal signals can be remove / re named if duplicated

All as expected.

If you want to look at an internal signal post P&R / synthesis , then you need to tell the synthesiser not to do anything with that signal,

as shown above, 

 

 

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

whats your experiance with simulation

what simulator are you using ?

The easy answer is looking at internal signals pre and post synthesis PAR is the same process.

BUT

Remember what the tools are doing,

   they are taking your code, synthesising and optimising it to fit into the FPAG and meet your constraints.

Rather similar to a C code, will be optimised , and possibly spread out over multiple cores of the CPU to optimise it.

 

So any given signal inside the code, might well have been absorbed or split into different signals,

At the least ,remember the tools do register push back / forward / duplication to improve performance,

 

The tools offer the options to selectively keep various parts of your code so you can check the signals,

  but note this probably not be an optimal P&R 

https://www.xilinx.com/support/answers/54699.html

https://www.xilinx.com/support/answers/54778.html

 

 

 

 

 

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pulsar
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Registered: ‎04-16-2015

Hello, drjohnsmith

Thank you for your reply.

>whats your experiance with simulation
Some years.
At all I had no problem with the Post Implementattion Timing Simulation
of the signals contained in the top entity.

>what simulator are you using ?
Vivado Simulator.
Testbench wrote on Verilog.

Some years ago I already asked about simulation of the internal signals and I got
following suggest:
"If you start a gate level timing simulation in Vivado,
you can navigate the design hierarchy and find signals of interest.
Once you find a signal you want to monitor, simply drag and drop it to the simulation wave window to observe the behavior and timing.
You may have to restart the simulation in order to get the behavior of a signal from the beginning,
once you add it to the wave windows"

I remember that I succesfully did it.
It's funny, but I can't remember how I did it.

I look internal signals of interest in the Netlist/Nets
after "Open Implemented Design".
It is the clock signals and they have the same names as in my source vhdl code.
But after Post Implementattion Timing Simulation I can not to get access to Netlist/Nets.

Best regards,
Viktor.

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drjohnsmith
Teacher
Teacher
461 Views
Registered: ‎07-09-2009

That all makes sence.

Top level signals, that basically connect to IO pins, 

    can not be optimised away, unless they are not used, so you will always see them.

Pre P&R, then the simulator is workgin on your design as is,

    no optimisation, no duplication , so all signals are there.

Post P&R / synthesis, there is optimisation

    thus internal signals can be remove / re named if duplicated

All as expected.

If you want to look at an internal signal post P&R / synthesis , then you need to tell the synthesiser not to do anything with that signal,

as shown above, 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

pulsar
Explorer
Explorer
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Registered: ‎04-16-2015

I asked: "How do add internal signals to the simulation wave window" I have remembered. 1. choose "uut" in "scope" => all available signals will appear in "object" 2. choise available signals (including internal) in "object" 3. add this signals to Wave. Attribute "dont_touch" really allow to see the name of the signals of interest in their original form. Thank you. Best regards, Viktor.

drjohnsmith
Teacher
Teacher
370 Views
Registered: ‎07-09-2009

Apologies for reading one thing and answering what I thought you meant, not what you said.

   well done for getting back

 

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pulsar
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Registered: ‎04-16-2015

You gave me usefull information.

Many thanks !