cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
ming2
Visitor
Visitor
20,758 Views
Registered: ‎01-05-2011

Simulation problems due to error

Jump to solution

hi, im new to this program. can anyone tell me what does these errors meant?

# ** Error: ../source/ringregosc.vhd(94): Actual (prefix expression) for formal "pre" is not a globally static expression.
# ** Error: ../source/ringregosc.vhd(102): Actual (prefix expression) for formal "clr" is not a globally static expression.
# ** Error: ../source/ringregosc.vhd(112): Actual (prefix expression) for formal "clr" is not a globally static expression.
# ** Error: ../source/ringregosc.vhd(122): Actual (prefix expression) for formal "clr" is not a globally static expression.

0 Kudos
1 Solution

Accepted Solutions
bassman59
Historian
Historian
27,051 Views
Registered: ‎02-25-2008

Ah, the classic example of something that's not globally static.

 

You can't use an operator (and NOT is an operator) in a port map.

 

 

----------------------------Yes, I do this for a living.

View solution in original post

12 Replies
awillen
Mentor
Mentor
20,738 Views
Registered: ‎11-29-2007

Could you please post the corresponding pieces of code? And please use the code environment (the black C on gray background).

 

 

Adrian



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
0 Kudos
bassman59
Historian
Historian
20,725 Views
Registered: ‎02-25-2008

"Globally static" means that the value of the expression is evaluated at elaboration time (roughly equivalent to link time in C). Sounds like you've got an expression or a function call in the port map of an entity instantiation.

 

Buy and read a good VHDL text.

----------------------------Yes, I do this for a living.
0 Kudos
ming2
Visitor
Visitor
20,706 Views
Registered: ‎01-05-2011

It is VHDL. In bold and of larger font size are the errors.

 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

SIGNAL bufcon0                  :  std_logic;  
   SIGNAL bufcon1                  :  std_logic;  
   SIGNAL bufcon2                  :  std_logic;  
   SIGNAL bufcon3                  :  std_logic;  


   COMPONENT FDCPE
   PORT(
        Q : OUT std_logic;
         C : IN std_logic;
         CE : IN std_logic;
         CLR : IN std_logic;
         D : IN std_logic;
         PRE : IN std_logic);  
   END COMPONENT;

 

BEGIN
   clock <= cntout ;

   flop1 : FDCPE
      PORT MAP (
         Q => bufcon1,
         C => '0',
         CE => '0',
         CLR => bufcon0,
         D => '0',
         PRE => NOT bufcon0);  
  

   flop2 : FDCPE
      PORT MAP (
         Q => bufcon2,
         C => '0',
         CE => '0',
         CLR => NOT bufcon1,
         D => '0',
         PRE => bufcon1);  
  

   flop3 : FDCPE
      PORT MAP (
         Q => bufcon3,
         C => '0',
         CE => '0',
         CLR => NOT bufcon2,
         D => '0',
         PRE => bufcon2);  
  

   flop4 : FDCPE
      PORT MAP (
         Q => bufcon0,
         C => '0',
         CE => '0',
         CLR => NOT bufcon3,
         D => '0',
         PRE => bufcon3);  

0 Kudos
bassman59
Historian
Historian
27,052 Views
Registered: ‎02-25-2008

Ah, the classic example of something that's not globally static.

 

You can't use an operator (and NOT is an operator) in a port map.

 

 

----------------------------Yes, I do this for a living.

View solution in original post

eteam00
Professor
Professor
20,692 Views
Registered: ‎07-21-2009

You can't use an operator (and NOT is an operator) in a port map.

You can use [~|!] modifier in Verilog port maps, if the port is a module input.

 

neener  neeener  neener  neener!

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
ming2
Visitor
Visitor
20,643 Views
Registered: ‎01-05-2011

Thanks to all! i've solve the problems.

0 Kudos
eteam00
Professor
Professor
20,639 Views
Registered: ‎07-21-2009

I'm curious, what was the solution (or solutions) ?

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
gatsby87
Visitor
Visitor
19,264 Views
Registered: ‎05-16-2013

I know this topic is old but even I had come across the same problem and the solution is to use a temporary signal. Declare a signal. Assign NOT value to it outside the port map. Then use that assigned signal value to map inside the port map.

0 Kudos
rcingham
Teacher
Teacher
19,248 Views
Registered: ‎09-09-2010
However, you can use an expression involving a function call. So, define a function called 'invert' or similar, and use that.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
gayathri90
Explorer
Explorer
7,711 Views
Registered: ‎01-18-2014
even i faced the same problem.

i synthesized my design and the simulated it. the error disappeared
0 Kudos
590 Views
Registered: ‎04-29-2021

Do you know how to fix it when its compiling but not letting me simulate my testbench? Its due to line 50 

sarahgrossman23_0-1619756366755.png

 

0 Kudos
maps-mpls
Mentor
Mentor
582 Views
Registered: ‎06-20-2017

Try not to concatenate on a port map.  

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***
0 Kudos