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Adventurer
Adventurer
4,777 Views
Registered: ‎07-27-2011

Simulation reference design for interrupts

Does Xilinx have a referance design for hanling interrupts on the PCIe root port when generated on the end port.

I am using Vivado with a Kintex 7 FPGA

 

Thanks

 

John

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Scholar sampatd
Scholar
4,768 Views
Registered: ‎09-05-2011

Re: Simulation reference design for interrupts

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