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Registered: ‎01-06-2009

Simulator Crashes if runtime is longer than 2000 ns

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I am running 10.1.03(nt).

 

I added a lot of functionality to my project, now Simulator (behaviorial) crashes 9 out of 10 times when I try to run it past 2000 ns.

 

Tried the obvious - Task Manager to clean up orphans, Clean up project files, removing code beyond 2000 ns in my VHDL test code.

 

Getting desperate here - got a whole project depending upon Xilinx and I can't keep ISE running.  Please help.

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Registered: ‎01-06-2009

Oh, Happy Day - I found a workaround that at least lets me continue my work!

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When the behavioral or PAR simulator crashes after spending 10 minutes compiling, all is not lost.  The waveforms are usually stored properly in the file isimwavedata.xwv - all you have to do is restart ISE and load this file to view it.

 

 Do the following:

 

Open Window's Task Manager, veiw the Processes tab.

End any "_pn.exe" processes.

End any process that looks like:

 

    Main_Main_sch_tb_isim_par.exe
    Main_Main_sch_tb_isim_beh.exe

Restart ISE.

Use "File/Open" to browse for "isimwavedata.xwv" in your project directory.

 

This makes the simulator usable now.  It took me three weeks to finally figure this out.  I opened a case file on this.  Of course the attachment portion of the case manager page on the Xilinx website crashes.  At least I got a laugh out of it.

 

I think that Xilinx uses the crash error window as an economical means of alerting you that a process is completed.  That saves resources by not having to come up with their own.  Save the planet, I always say!

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10,859 Views
Registered: ‎01-06-2009

Re: Simulator Crashes if runtime is longer than 2000 ns

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More info on problem with Simulator crashes on long runtime:

 

I deleted several waveforms and now it will simulate to 5000 ns.

 

Memory problem, quantity problem, or issue with a waveform?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-15-2007

Re: Simulator Crashes if runtime is longer than 2000 ns

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Mike,

 

How many signals do you typically display on the waveform?  I've only seen these type of issues if you have a large number of signals displayed (near 100).

 

Also, which version of the tools are you using?

 

-edv

Eddie
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Registered: ‎01-06-2009

Re: Simulator Crashes if runtime is longer than 2000 ns

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I probably display about 20 or so - of course some of those are busses and may count as more.

 

I have found some really odd tricks that sort of help.  Sometimes the simulator will run fine, then I will change something slightly in the project and it crashes again.

 

Here is some more info:

 

If the simulator crashes, I reduce the time and run again, then remove most of the signals.  Then I run again for the longer simulation time and re-add the signals.  Afterwards, the simulator seems to work if I just double click on the process "Simulate Behavioral Model" instead of right clicking and choosing "Run All".  After the simulator runs without crashing, I can and sometimes must use the "Run All" option - sometimes this will work without crashing.

 

Sometimes the simulator will crash the first time I run it after starting the ISE the first time after a reboot.  After restarting ISE again, the simulator will run thereafter until unspecified changes are made to the project.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-15-2007

Re: Simulator Crashes if runtime is longer than 2000 ns

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Mike,

 

I apologize for the inconvenience.  I don't have too many suggestions to have you refrain from running into these sort of issues with the simulator.  But here are a few:

 

  • Make sure you are running the ISE tools on a supported Operating System 
  • Make sure you have memory available for the software (Limit the use of virtual memory)
  • Make sure you close the software cleanly (via File --> Exit, or "X" icon on window)


For 11.1, we have worked in developing a stronger and more stable simulator.  I invite you to give it a try once it is made once ISE Design Suite 11.1 is made available this Spring.

 

 

Eddie
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Registered: ‎01-06-2009

Re: Simulator Crashes if runtime is longer than 2000 ns - latest update

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Seems to crash when I change the Testbench simulation file.

 

I can change the various VHDL modules with no problem.

 

Solution so far seems to be after crash to use Task Manager to stop _pn and any simulation process (look like Main_main_sch_tb_isim_beh.exe) running.  Then restart, clean up project files, and double click on "Simulate Behavioral Model".

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Registered: ‎01-06-2009

Re: Simulator Crashes if runtime is longer than 2000 ns - latest update #2

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I paid $3500 to get the full version of Foundation and ISIM.

 

Guess what?  Still crashes!

 

Takes 10 minutes to compile just to find out it's going to crash.  Again and again.

 

If I reduce simulation time or number of waveforms displayed, works fine.

 

Seems like if I get it to run with a short time, it will then run with a longer time if nothing is changed in code - haven't totally verified this yet.

 

I'm not displaying more than 30 or 40 signals.

 

I can't believe no one else is having this problem.  Any one?

 

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Historian
Historian
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Registered: ‎02-25-2008

Re: Simulator Crashes if runtime is longer than 2000 ns - latest update #2

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If you are doing pre-synthesis/fit functional simulation, dump ISIM and use ModelSim. The free starter edition should handle pretty much anything you're doing, unless you're big into BFM with EDK.

 

If you have proper timing constraints, there is no need to do a post-placer timing simulation.

 

-a

----------------------------Yes, I do this for a living.
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Registered: ‎01-06-2009

Re: Simulator Crashes if runtime is longer than 2000 ns - latest update #2

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Here's my problem(s):

 

I don't have time to switch over and learn a new simulator until mid year.

 

I don't have a clue about proper timing constraints.  I've read the Xilinx manuals - I think I might understand Clock to Pad - and that's it.

 

So my address line zero is violating a setup constraint in respect to my clock.  Do I constrain the address line, the clock line, or both?  How do I contrain two signals to ensure that skew doesn't screw things up?

 

Know a good book specific to Xilinx constraints?

 

The tutorial is a joke:  "put value here - you are done".   Huh?  Why did I put the value there?

 

The manuals are worse: "put very complicated value here.  Does very complicated thing.  Or maybe not.".

 

I recently began reading "Advanced FPGA Design" by Steve Kilts - it's already helped, but zero info regarding timing constraints.

 

What is needed is a cause and effect explanation:

 

"if you receive this warning, you may fix it by applying this type of constraint to the signal".

 

Yes, I am a neophyte.  But I've been around a while and I've never seen anything like this.  Apparently some of you have some secrets the rest of us are not privy to.  It sounds like you are skipping the post route timing simulation, which the Xilinx manual says is a bad idea.  Who's right?

 

How would I know if my timing constraints are correct without corrective feedback?  Are you guys just plugging it into the silicon and seeing if it works?  The problem is the equipment I am designing for costs 1/2 million dollars.  My end users are not appreciative of a daily crash because the chip heated up and fell out of timing specs.

 

What's the secret here?  I feel like I am chipping on a piece of steel.  I can't find any of the warnings in any manual.

 

By the way, I paid the $3500 bucks to upgrade just so I could run the PAR simulator.  It still crashes.

 


Thanks for the input.

 

 

 

 

 

 

 

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12,696 Views
Registered: ‎01-06-2009

Oh, Happy Day - I found a workaround that at least lets me continue my work!

Jump to solution

 

When the behavioral or PAR simulator crashes after spending 10 minutes compiling, all is not lost.  The waveforms are usually stored properly in the file isimwavedata.xwv - all you have to do is restart ISE and load this file to view it.

 

 Do the following:

 

Open Window's Task Manager, veiw the Processes tab.

End any "_pn.exe" processes.

End any process that looks like:

 

    Main_Main_sch_tb_isim_par.exe
    Main_Main_sch_tb_isim_beh.exe

Restart ISE.

Use "File/Open" to browse for "isimwavedata.xwv" in your project directory.

 

This makes the simulator usable now.  It took me three weeks to finally figure this out.  I opened a case file on this.  Of course the attachment portion of the case manager page on the Xilinx website crashes.  At least I got a laugh out of it.

 

I think that Xilinx uses the crash error window as an economical means of alerting you that a process is completed.  That saves resources by not having to come up with their own.  Save the planet, I always say!

View solution in original post

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Xilinx Employee
Xilinx Employee
4,713 Views
Registered: ‎08-15-2007

Re: Oh, Happy Day - I found a workaround that at least lets me continue my work!

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Mike,

 

We apologize for the inconveniences this issue has caused.

 

In the next version of ISim (11.1) we'll be introducing a new flow that is independent of the ISE interface, offering much better processing and graphical performance.  The 11.1 tools will be made available around late April.  We encourage you to give the new version a try and share your feedback.

 

 

 

Eddie
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Explorer
Explorer
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Registered: ‎11-13-2007

Re: Oh, Happy Day - I found a workaround that at least lets me continue my work!

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New flow...lots of new bugs.

 

I just received a survey asking a bunch of question about Altera's Quartus and Xilinx's ISE. I have to say I gave a much lower score to ISE (I really wanted it to be for EDK, which stinks IMO), but nevertheless it relayed my dissatisfaction with Xilinx tools in general.

 

Mike, I have the same "what in the hell?" feelings you do about this. I just got too tired to keep complaining about it.

Your comments on the tutorial are spot on.

 

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Registered: ‎01-06-2009

Re: Oh, Happy Day - I found a workaround that at least lets me continue my work!

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Yes, it's insane.

 

After switching to ModelSim for my simulation, most of my immediate problems went away.  It never crashes and it only took a few minutes to learn the basics.

 

Here are the most common answers I have received from Xilinx and others:

 

1) You're using  schematic for your top level?  That's your whole problem!  Quit that.

1a) You're using VHDL?  That's your whole problem!  Quit that.

1b) You're using Verilog?   That's your whole problem!  Quit that.

1c) You're using ISE?  (you know the drill)

2) Ignore those errors and warnings.  And those.  And those.  And those others.  Yeah, it'll all work - go ahead and design your board.

3) You're doing PAR simulation?  NOBODY does that.  (even though the Xilinx manual says it is imperative to do so)

4) The attribute is not being applied because it's not attached to a component in a flattened design.  Or because it's not an IOB.  Or, or, or....

5) Read the manuals.  All of them.  Every single bit of them.  Ignore all the stuff that's not explained.  If it's not explained, you don't need it.

6) Mine doesn't crash.  I don't know why yours does.  Are you using Windows?  That's your whole problem!

7) Yes, the software costs $3,500.  How else could we pay top-notch programmers to insert one bug per function?   Don't even ask about the crashes.

 

And the number one answer is....

 

8) That bug will be fixed in ISE 11.1

 

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