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juanzemanate
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Registered: ‎05-19-2013

Simulink system period and FPGA clock period

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Hello!!

 

I've read some posts related to this question, but I'm a little confused.


If I have a simulink system period of 1/20, a FPGA clock period of 10 ns and a block with a sample period of 2. What is the sample rate of the block in hardware?.
If the simulink system period doesn't affect the sample rate of the block in hardware, the sample rate will be 50Mhz. Is it correct or there is some relation in hardware (between simulink system period and FPGA clock period).

 

Thanks a lot.

 

 

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bwiec
Xilinx Employee
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Registered: ‎08-02-2011

I would also recommend that you have a look at the demos provided with sysgen. Start playing with them. Change the rates and see how things react.

www.xilinx.com

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bwiec
Xilinx Employee
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Registered: ‎08-02-2011

Have you read the 'Timing and Clocking' section here:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/sysgen_user.pdf

www.xilinx.com
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juanzemanate
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Registered: ‎05-19-2013

Many thanks for your reply.

Yes I did, but I can't get the idea. I know that in simulation If I have a simulink system period of 1/20, a FPGA clock period of 10 ns and a block with a explicit sample period of 2, the sample rate would be 1/40. But I don't know how it works in hardware.

The PDF says that System Generator employs two user-specified values : the Simulink system period and FPGA clock period. "If p represents the Simulink system period, and c represents the FPGA system clock period, then something that takes kp units of time in Simulink takes k ticks of the system clock (hence kc nanoseconds) in hardware".

According to the above paragraph,how can I get the value "k"?.What does this value represents?
I can't see the relation betwen Simulink system period and FPGA clock period.

 

Thanks

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Yeah... that description is a bit confusing.

 

The idea is that the simulink system period provides normalization for the rates in the design so that things can be more easily resolved in simulink.

 

The easiest way for me to think about it is through a very simple example:

FPGA clock period = 10ns (100MHz)

Simulink System Period = 1

Gateway In Sample Period = 1

 

The FPGA clock period gives you the actual constraint that is going to be written out. It expects to be run at a clock rate of 10ns on the board. Now, this 10ns is normalized to 1 in simulink land (Simulink System Period). So now, any time you see a 1 for the sample period of some block (Gateway In Sample Period), that corresponds to 10ns in hardware time.

 

So the Gateway In Sample Period will end up being 10ns on the board.

 

If you change the Gateway In Sample Period to 2 this will correspond to a 20ns sampling period on the board.

 

By default (for the most use cases), sysgen will only ever use 1 clock and the lower rates will be implemented with clock enables.

www.xilinx.com
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bwiec
Xilinx Employee
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Registered: ‎08-02-2011

I would also recommend that you have a look at the demos provided with sysgen. Start playing with them. Change the rates and see how things react.

www.xilinx.com

View solution in original post

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juanzemanate
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Registered: ‎05-19-2013

Thank you I will ckeck the demos. I understand your example.

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ywu
Xilinx Employee
Xilinx Employee
8,710 Views
Registered: ‎11-28-2007

Take a look at the blog below and let me know if it helps:

 

DDS in System Generator: how to set up periods?

 


@juanzemanate wrote:

Thank you I will ckeck the demos. I understand your example.




Cheers,
Jim
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