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Explorer
Explorer
1,492 Views
Registered: ‎03-27-2017

System Verilog xvlog trouble

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I'm trying to compile the following system verilog macro definition for my test bench:

 

`define test_clock(frequency) \
  localparam FREQUENCY = frequency; \
  localparam HALF_CYCLE = 500000000/(FREQUENCY/1000); \
  localparam CYCLE = 2*HALF_CYCLE; \
  reg             clock_enable; \
  wire            clock; \
  initial begin clock_enable = `false; #1; clock_enable = `true; end \ // send a positive edge to clock enable
  SIM_Clock #( \
    .FREQUENCY( FREQUENCY), \
    .PHASE(     0) \
  ) clock_source ( \
    .enable(    clock_enable), \
    .clock(     clock) );

I'm getting syntax errors due to the backslashes, but I believe these are correct (though I have a limited knowledge of system verilog). Could anyone tell me what's wrong with the above code?

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Observer
Observer
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Registered: ‎08-29-2017

Re: System Verilog xvlog trouble

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It can't really process your line numbers in a macro because the parser sees code that's all on the same line unless the team writing the lexer and parser have really put some time into it. So you often will find for macros that you get errors at the end that are really due to issues in the middle. 

For problems like this, I'd try writing it all on one line first and then, only after that works, split the lines with a back-slash. If you still have problems after my suggestion, try taking out pieces one-by-one until you can isolate which piece is causing the problem.

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Observer
Observer
1,477 Views
Registered: ‎08-29-2017

Re: System Verilog xvlog trouble

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Try removing the comment at the end of your line 7.

If they followed the C conventions, then the backslash essentially means ignore the following character (a newline) so the lexer which feeds tokens to the parser will not pass the backslash or the following character to the parser. 

Your code would have an end-of-line comment in the middle of a line of code causing the rest of the macro to look like a comment.

In C this would be a problem. I'm not certain about SystemVerilog's preprocessor but it is worth a try.

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Explorer
Explorer
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Registered: ‎03-27-2017

Re: System Verilog xvlog trouble

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Thanks for the tip @inflector.

 

More specifically, I'm getting errors from the backslashes after the lines of code for the SIM_Clock instantiation.

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Observer
Observer
2,231 Views
Registered: ‎08-29-2017

Re: System Verilog xvlog trouble

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It can't really process your line numbers in a macro because the parser sees code that's all on the same line unless the team writing the lexer and parser have really put some time into it. So you often will find for macros that you get errors at the end that are really due to issues in the middle. 

For problems like this, I'd try writing it all on one line first and then, only after that works, split the lines with a back-slash. If you still have problems after my suggestion, try taking out pieces one-by-one until you can isolate which piece is causing the problem.

View solution in original post

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Explorer
Explorer
1,458 Views
Registered: ‎03-27-2017

Re: System Verilog xvlog trouble

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Genius @inflector! Thanks!

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