03-01-2017 07:54 PM - edited 03-01-2017 07:54 PM
I've got a Vivado 2016.4 block diagram containing custom logic as well as a FIR Compiler 7.2 block. I generated output products for it and wanted to simulate it as a black box in System Generator. It failed, and the elaboration log spat out a Xilinx hardocded path that screwed everything up. Here is the contents of elaborate.log:
Vivado Simulator 2016.4 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 4ed16aa075984127a4da5573e297555a --debug off --dll --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot Reloadable_FIR_Top_wrapper_wrapper_behav xil_defaultlib.Reloadable_FIR_Top_wrapper_wrapper xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-2553] file 'filepointer' is not open [/wrk/2016.4/nightly/2016_12_14_1733598/packages/customer/vivado/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd:4366] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
03-01-2017 08:39 PM - edited 03-01-2017 09:20 PM
Absolutely can share the project, I just sent you a PM. Let me know if you want it another way.
I made sure all of the paths work and saved everything to a tarball. It's not very big - in testing I cut out everything unrelated to the error, so the Vivado block basically contains the FIR compiler and a wrapper, nothing else.
04-26-2017 02:25 PM
07-10-2017 09:43 AM
Has this issue been resolved?
I'm having a similar problem in Vivado 2017.2 using the sysgen black box with a CFR module.
07-10-2017 09:50 AM - edited 07-10-2017 09:50 AM
10-22-2018 02:13 AM
I've got the same problem here with Vivado 2017.4. Still no response from Xilinx?
10-22-2018 03:17 AM
10-22-2018 10:53 PM
10-24-2018 03:40 AM - edited 10-24-2018 03:41 AM
Do you have .slx for the design. I am getting different set of errors for the code in the zip file.
10-25-2018 12:07 AM
11-05-2018 12:13 AM
I'm still looking forward to a resolution. Xilinx, please comment further
11-19-2018 05:09 AM
"The Xilinx Community Forums is here to help! Ask questions and collaborate with Xilinx experts to get the solutions you need."
I seem to be very much alone when using the Xilinx Forums :(
11-19-2018 05:20 AM
Yea, we all feel that way... Getting Xilinx to fix something when the forum is the only link to them just doesn't work.
Gotta be the kind of large customer they listen to :)
11-20-2018 03:30 AM
I got this example working by copying fir_compiler_1.mif file to simulationRun folder, the elaboration just did not find the coefficient file.