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Adventurer
Adventurer
580 Views
Registered: ‎11-08-2017

[SystemVerilog] Array Declaration cases

Hi All,

Is there a difference in the following declarations:

case1:
reg [3:0][7:0] abc;
case2:
reg [3:0] abc [7:0];
case3:
reg abc [3:0][7:0];

What's the difference?

Thank you!

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1 Reply
Moderator
Moderator
541 Views
Registered: ‎05-31-2017

Re: [SystemVerilog] Array Declaration cases

Hi @dmitryl_home,

 

case1: reg [3:0][7:0] abc;

The above declaration represents a Packed array and the above declaration treats the 32 bits present in the array as 4 groups of 8 bits each. In memory all these bits are packed together as 32 bits.

 

case2: reg [3:0] abc [7:0];

This sort of declaration generally represents an unpacked array and the above declaration treats the 32 bits present in the array as 8 groups of 4 bits each. In memory these arrays are stored using regular addressing rather than packed together in a single address.

 

case3: reg abc [3:0][7:0];

Which in general is a multi dimension array.

 

Thanks & Regards,
A.Shameer