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3,299 Views
Registered: ‎10-08-2010

Test bench inputs large circuit testing

Hi,

 

I want to test a combinational circuit with 36 inputs for all possible input combinations. I have written a for loop in the testbench, but apparently the loop variable is only allowed to be 32 bits (int) even though I explicitly declare it as a reg of 36 bits. I am using Xilinx ISE 9.2i simulator ISIM for the simulations.

 

Is it possible to test for this many possible inputs? Please advice.

 

I really appreciate your inputs and wait in anticipation.

 

Thanks,

Rizwan 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

2^36 is a big number  68,719,476,736 to be exact.  If your simulation can get 100,000 vectors/sec it would take 7.95 days to complete.

 

If you still want to go ahead and do this then I would suggest that you use two loops.  The inner loop covers bits 0-31 (0 to 4,294,967,295) and the outer loop covers the last 4 bits of 32-35 (0 to 15). 

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Teacher
Teacher
3,283 Views
Registered: ‎08-14-2007

Hi Rizwan,

that will be a looooong simulation.

 

How about not using loops.

 

use ieee.numeric_std.all;

...

signal count36 : unsigned(35 downto 0) := (others => '0');  -- initialize 36 bit vector to zero

...

process

  count36<= count36 + 1;

  wait for 100ns;

end process;

 

 

then you can assignit e.g like this:

  DUT_In <= std_logic_vector(count36);

 

or put it in the port map of the DUT instanciation.

 

Have a nice simulation

   Eilert

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