03-03-2011 06:45 PM
I want to test a combinational circuit with 36 inputs for all possible input combinations. I have written a for loop in the testbench, but apparently the loop variable is only allowed to be 32 bits (int) even though I explicitly declare it as a reg of 36 bits. I am using Xilinx ISE 9.2i simulator ISIM for the simulations.
Is it possible to test for this many possible inputs? Please advice.
I really appreciate your inputs and wait in anticipation.
03-03-2011 07:05 PM
2^36 is a big number 68,719,476,736 to be exact. If your simulation can get 100,000 vectors/sec it would take 7.95 days to complete.
If you still want to go ahead and do this then I would suggest that you use two loops. The inner loop covers bits 0-31 (0 to 4,294,967,295) and the outer loop covers the last 4 bits of 32-35 (0 to 15).
03-04-2011 12:08 AM
that will be a looooong simulation.
How about not using loops.
signal count36 : unsigned(35 downto 0) := (others => '0'); -- initialize 36 bit vector to zero
count36<= count36 + 1;
wait for 100ns;
then you can assignit e.g like this:
DUT_In <= std_logic_vector(count36);
or put it in the port map of the DUT instanciation.
Have a nice simulation