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Explorer
Explorer
24,526 Views
Registered: ‎03-08-2012

The difference between reg, wire and logic in SystemVerilog

Just as the title says, The difference between 'reg', 'wire' and 'logic' in SystemVerilog, this is the eternal problem in Verilog and SystemVerilog learning~~~~

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Moderator
Moderator
24,523 Views
Registered: ‎06-05-2013

Re: The difference between reg, wire and logic in SystemVerilog

Systemverilog is super set of verilog so it has all the data types which are there in verilog.
Logic is a systemverilog data type which can be used in place of reg & wire. Since it is confusing which one to declare as reg or wire in verilog so they have introduced logic as new data type in systemverilog. Tool will automatically interprets its behavior according to its usage.

Check the below white paper for detailed description http://www.eda.org/sv-bc/hm/att-0238/01-Logic_20021209.PDF

I hope this may help you.

Regards,
Harry

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Moderator
Moderator
24,506 Views
Registered: ‎04-17-2011

Re: The difference between reg, wire and logic in SystemVerilog

Xilinx Synthesis User guide has a section for Data Types of SV: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf
Additional Doulos has excellent content for begineers: https://www.doulos.com/knowhow/sysverilog/ .
Regards,
Debraj
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