04-27-2014 09:34 PM
Just as the title says, The difference between 'reg', 'wire' and 'logic' in SystemVerilog, this is the eternal problem in Verilog and SystemVerilog learning~~~~
04-27-2014 09:41 PM - edited 04-27-2014 09:42 PM
Systemverilog is super set of verilog so it has all the data types which are there in verilog.
Logic is a systemverilog data type which can be used in place of reg & wire. Since it is confusing which one to declare as reg or wire in verilog so they have introduced logic as new data type in systemverilog. Tool will automatically interprets its behavior according to its usage.
Check the below white paper for detailed description http://www.eda.org/sv-bc/hm/att-0238/01-Logic_20021209.PDF
I hope this may help you.
04-28-2014 03:47 AM