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rva.raghav
Observer
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Registered: ‎02-24-2015

Timing Diagram

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I have given the timing diagram for my Binary Sequence detector for the sequence "1010".Its working correctly,but why is the output lasts 5ns less than the input.Can I proceed to do it on the hardware.
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gszakacs
Professor
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Registered: ‎08-14-2007

@rva.raghav wrote:

Is this code perfect or some changes have to be made ?

 


Your original question was why the output pulse width is only half as long as a bit period.  If this is acceptable then the code is OK.  If you need the output pulse to last for exactly one bit period then you either need to make sure that the input signal "din" is changing only on the rising edge of the clock, or you need to add a register (flip-flop) to your "y" output.  As coded, the "y" output is purely combinatorial, meaning it is made from gates and not flip-flops.  That's why it changes with "din" as well as with the current state.  I would suggest using the "View RTL Schematic" process under Synthesis in the ISE GUI.  This shows you a gate-level schematic of what your code represents in hardware.

-- Gabor

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vijayak
Xilinx Employee
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Registered: ‎10-24-2013
Hi,
"but why is the output lasts 5ns less than the input"...What do you mean by this statement? can you please elaborate?
Thanks,Vijay
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rva.raghav
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Why the output lasts only for a short period compared to the input ?
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aher
Xilinx Employee
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Registered: ‎07-21-2014
Hi,

can you please share your code here?

thanks,
Shreyas
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bassman59
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Registered: ‎02-25-2008

Without seeing your PROPERLY FORMATTED, READABLE code, it is impossible to say what's going on.

----------------------------Yes, I do this for a living.
gszakacs
Professor
Professor
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Registered: ‎08-14-2007

The output is doing exactly what you asked it to do.  In your code for state 3:

 

   S3: if (din == 1'b0)
          begin
         nst = S2;
          y=1'b1;
          end
       else
          begin
          nst = S1;
          y=1'b0;
          end

 

you are inside a combinatorial process.  You say that while the current state is S3, y is equal to the inverse of din.  In your simulation din is changing on the falling edge of the clock midway through state S3.  This would be easier to see if you also showed cst in the wave view.

 

If you don't want your output variables to change mid-cycle, they should be registered in a clocked process.  In fact, most serious FPGA designers these days use a single clocked process for their finite-state machines.  The classification of state machines as Mealy or Moore really is of no interest to the end goal of making logic that actually works.  I understand that this is an academic undertaking for you, but it would really be good if schools taught logic design techniques that are more in line with modern design practices.

-- Gabor
rva.raghav
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This is the code.

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rva.raghav
Observer
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Thanks for your suggestions Gabor.But I dont understand what you are saying.Can you explain it a little clearly.
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rva.raghav
Observer
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Code is attached Shreyas.

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rva.raghav
Observer
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The code is attached.

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bassman59
Historian
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rva.raghav wrote:

The code is attached.


Nobody is going to open a potentially virus-laden document from the Internet.

 

How about just posting the code in this forum directly, using the "Insert Code" option?

----------------------------Yes, I do this for a living.
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rva.raghav
Observer
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module melfsmolp(din, reset, clk, y); output reg y; input din; input clk; input reset; reg [1:0] cst, nst; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @(cst or din) begin case (cst) S0: if (din == 1'b1) begin nst = S1; y=1'b0; end else begin nst = cst; y=1'b0; end S1: if (din == 1'b0) begin nst = S2; y=1'b0; end else begin nst = cst; y=1'b0; end S2: if (din == 1'b1) begin nst = S3; y=1'b0; end else begin nst = S0; y=1'b0; end S3: if (din == 1'b0) begin nst = S2; y=1'b1; end else begin nst = S1; y=1'b0; end default: nst = S0; endcase end always@(posedge clk) begin if (reset) cst <= S0; else cst <= nst; end endmodule
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rva.raghav
Observer
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Registered: ‎02-24-2015
module melfsmolp(din, reset, clk, y);
output reg y;
input din;
input clk;
input reset;
reg [1:0] cst, nst;
parameter S0 = 2'b00,
          S1 = 2'b01,
          S2 = 2'b10,
          S3 = 2'b11;
always @(cst or din)
 begin
 case (cst)
   S0: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b0;
          end
      else
          begin
           nst = cst;
          y=1'b0;
          end
   S1: if (din == 1'b0)
          begin
        nst = S2;
          y=1'b0;
          end
       else
          begin
           nst = cst;
          y=1'b0;
          end
   S2: if (din == 1'b1)
          begin
         nst = S3;
          y=1'b0;
          end    
            else
          begin
           nst = S0;
          y=1'b0;
          end
   S3: if (din == 1'b0)
          begin
         nst = S2;
          y=1'b1;
          end
       else
          begin
          nst = S1;
          y=1'b0;
          end
   default: nst = S0;
  endcase
end
always@(posedge clk)
begin
           if (reset)
             cst <= S0;
           else
             cst <= nst;
end
endmodule











 

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gszakacs
Professor
Professor
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Registered: ‎08-14-2007

@rva.raghav wrote:
Thanks for your suggestions Gabor.But I dont understand what you are saying.Can you explain it a little clearly.

(scratching head...) I thought it was pretty clear.  What exactly did you have trouble understanding?  The bit about the combinatorial logic?  How to add your signals to the waveform view?  Single process finite-state machines?

-- Gabor
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rva.raghav
Observer
Observer
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Registered: ‎02-24-2015

Is this code perfect or some changes have to be made ?

 

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gszakacs
Professor
Professor
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Registered: ‎08-14-2007

@rva.raghav wrote:

Is this code perfect or some changes have to be made ?

 


Your original question was why the output pulse width is only half as long as a bit period.  If this is acceptable then the code is OK.  If you need the output pulse to last for exactly one bit period then you either need to make sure that the input signal "din" is changing only on the rising edge of the clock, or you need to add a register (flip-flop) to your "y" output.  As coded, the "y" output is purely combinatorial, meaning it is made from gates and not flip-flops.  That's why it changes with "din" as well as with the current state.  I would suggest using the "View RTL Schematic" process under Synthesis in the ISE GUI.  This shows you a gate-level schematic of what your code represents in hardware.

-- Gabor

View solution in original post

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