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Explorer
Explorer
3,125 Views
Registered: ‎03-13-2012

Timing or Post-route incorrect simulation result.

Dear all,

I am having problem in Timing simulation (post-route simulation). I have pasted the relevant items below.

I am having the following warning and I guess because of this I am not able to get the required results. It will be really helpful if some one can decode
this warning, i.e. what is $setuphold and things in bracket. Well I have concepts regarding setup and hold time but I cannot understand what the error here means

 

WARNING: at 118166 ps: Timing violation in /stim_count/uut/out_2/ $setuphold( CLK:118166 ps, I:117651 ps,536 ps,-344 ps)

My design is a simple counter as follows

Code:
module signed_counter(
    input clk,
    input rst,
    input signed [7:0] num1,
    input signed [7:0] num2,
    output reg [8:0] out
    );

always@(posedge clk)
begin
	if(rst) out <=9'b0;
	else  out <= num1 + num2;	
end

endmodule

the simulation file is as follows

Code:
`timescale 1ns / 1ns

module stim_count;

	// Inputs
	reg clk;
	reg rst;
	reg [7:0] num1;
	reg [7:0] num2;

	// Outputs
	wire [8:0] out;

	// Instantiate the Unit Under Test (UUT)
	signed_counter uut (
		.clk(clk), 	.rst(rst), 
		.num1(num1), .num2(num2), 
		.out(out)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1; 
		num1 = -100;		num2 = -7;
		# 15 rst=1'b0;
#25	num1 = -100;		num2 = -7;
#25	num1 = -100;		num2 = -128;
#25	num1 =  127;		num2 = 127;
#25	num1 =  108;		num2 = 119;
#15	num1 = -128;		num2 = -128;		
	end
      
		always #5 clk = ~clk;
endmodule

The resulting waveform is here.

11.PNG

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1 Reply
Xilinx Employee
Xilinx Employee
3,122 Views
Registered: ‎07-16-2008

Re: Timing or Post-route incorrect simulation result.

The warning suggests that timing violation is detected for instance "/stim_count/uut/out_2".

You can check SDF file, search the instance and see the required $setuphold value for the I input with regards to CLK.

 

I think 536 ps is the expected setup value while observed value is 515 ps (118166 - 117651).

 

Have you specify PERIOD constraint in UCF? We recommend that you do post-PAR static timing analysis for sign-off.

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