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asim2010
Visitor
Visitor
3,504 Views
Registered: ‎09-29-2010

Timing simulation problems

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Hello,

I have design which uses MCB ,core generator trimac soft core . I tried to create the netlist for timing simulation .

I am using ISIM full version. The netlist gets created , all the modules get compiled but the isim gui opens and issue a win32 exception. It does not get lauch and exits.

 

How to get read of this issue?

 

Secondly, How to simulate(post-route simulation)  the lower level modules of the same design.

I tried to create the test bench of the lower module and tried to simulate it but it issued an error " .sdf cannot be read or is not created". I think this is because the signal name of the lower level modules gets changed after P&R.

How to get read fo this issue?.

 

Would really appreciate if some one can help.

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edv
Xilinx Employee
Xilinx Employee
4,268 Views
Registered: ‎08-15-2007

Hello,

 

In regards to the win32 exception, does the simulator launch successfully for behavioral simulations?  If so, you may be running out of memory.  Timing simulations require a large amount of memory and, for some designs, a 32-bit system is not sufficient (that is, you'll have to run the simulation using 64-bit OS).  Enabling 3GB memory usage may help.  

 

In regards to the ".sdf cannot be read or is not created", this probably occurs because you are attempting to run a post-par simulation on a module that has not been taken through the implementation flow.  That is, in order to do a "post-Place and Route" simulation of your sub-module, you *have* to take the submodule through Synthesis-Translate-Map-PAR.

 

If you are interested on studying signals from your sub-module during timing simulation, your best bet is to run a Post-PAR simulation on your top level design as usual but enable "keep hierarchy".  That way the hierarchy is not flattened and can be used in timing simulation to review signals at the desired hierarchy level.

 

To do so, review the "Keep Hierarchy" settings in your synthesizer as well as Map.  For XST, set to "Yes", and in Map, disable "Allow Logic optimizations across hierarchies".

 

Hope this helps.

Eddie

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edv
Xilinx Employee
Xilinx Employee
4,269 Views
Registered: ‎08-15-2007

Hello,

 

In regards to the win32 exception, does the simulator launch successfully for behavioral simulations?  If so, you may be running out of memory.  Timing simulations require a large amount of memory and, for some designs, a 32-bit system is not sufficient (that is, you'll have to run the simulation using 64-bit OS).  Enabling 3GB memory usage may help.  

 

In regards to the ".sdf cannot be read or is not created", this probably occurs because you are attempting to run a post-par simulation on a module that has not been taken through the implementation flow.  That is, in order to do a "post-Place and Route" simulation of your sub-module, you *have* to take the submodule through Synthesis-Translate-Map-PAR.

 

If you are interested on studying signals from your sub-module during timing simulation, your best bet is to run a Post-PAR simulation on your top level design as usual but enable "keep hierarchy".  That way the hierarchy is not flattened and can be used in timing simulation to review signals at the desired hierarchy level.

 

To do so, review the "Keep Hierarchy" settings in your synthesizer as well as Map.  For XST, set to "Yes", and in Map, disable "Allow Logic optimizations across hierarchies".

 

Hope this helps.

Eddie

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asim2010
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3,487 Views
Registered: ‎09-29-2010

Yes, The simulator launch successfully for behavioral simulation.

I will try the same design on windows 7 64 bit ,4GB box.

 

Yes, I was trying to run post -par simulation of a sub module. I m at the last step of the whole design and if i enable keep heirarchy the synthesis gets changes,timing constraints has to be changed and so on... but anyways if the timing simulation of the whole design works..i dont need to run PAR simulation for sub modules...

 

Thanks for your help.. I will let you know if i have any problems further..

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