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6,193 Views
Registered: ‎04-01-2014

Triangular Wave Form

This is my code to generate a triangular wave form, but how I do to try it in Xilinx ISE Project Navigator in the simulator? I don't have the Nexys 3 because my university is close for the Holy Week, please let me know if my code works!

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Triangular is
port(
clk : in std_logic;
n : in integer;
op : out integer
);
end Triangular;

architecture Behavioral of Triangular is
begin
process(clk)
variable count : integer:=0;
variable s : std_logic:='0';
begin
if RISING_EDGE(clk) then
count := count + 1;
end if;
if(count>=n/2) then count:=0;
s := NOT s;
end if;
if(s='0') then
op <= count*255/n;
else
op <= 127-count*255/n;
end if;
end process;
end Behavioral;

 

Thanks for your help! :)

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2 Replies
Advisor eilert
Advisor
6,181 Views
Registered: ‎08-14-2007

Re: Triangular Wave Form

Hi,

you don't need a board to do simulations.

Even the ISIM light that comes with the webpack is sufficient for such a small model.

 

The code might actually work for simulation, maybe rising_edge should be written in lower case letters. (emacs had problems with the formatting)

 

The code won't synthesize  since dividing can only be done by some 2^n value, not just any integer.

Also there are several other minor issues:

(unconstrained integer ports,  lots of combinatorical stuff behind the synchronous assignment etc.)

 

Maybe you should take a look at the ISE language templates for a loadable up/down counter.

Also learning about signed and unsigned data types (numeric_std) can be helpful.

 

Have a nice synthesis

  Eilert

 

 

 

 

 

 

 

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Moderator
Moderator
6,169 Views
Registered: ‎04-17-2011

Re: Triangular Wave Form

Check out the ISIM Tutorial: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/ug682.pdf
Regards,
Debraj
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