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rmogster
Observer
Observer
1,506 Views
Registered: ‎12-12-2017

Trouble finding IP core for simulation

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Hi,

 

I am having a problem simulating a new design.  I created a Xilinx project.  I brought in the PCIe core. I had the Vivado tool create the example project for the PCIe IP core.  I also had the Vivado tool compile all the libraries for simulation with the Modelsim tool.  I put the compiled libraries in the folder Xilinx\Sim_libs.  The tool compiled all the libraries there, and also added a modelsim.ini file.  I created a new modelsim simulation.  I had Modelsim use the ini file in Xilinx\Sim_libs.  I brought in all the source files from the folder "imports", since this is where Vivado put all the generated verilog files.  I compiled all the source files, including the TB file Vivado generated "board.v". 

I started the simulation using the following on the command line: (this got rid of some earlier errors)

vsim work.board -L unisims_ver  -L secureip 

 

I get the following error:

                Instantiation of 'pcie3_ultrascale_0' failed. The design unit was not found.

 

Has you seen this problem before, and how do I fix it?  I am sure if I add the right lib file this will go away, but I don’t know which folder has the PCIe IP core.

 

Thank you,

Rolf

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amaccre
Moderator
Moderator
1,748 Views
Registered: ‎04-24-2013

Hi @rmogster,

 

Which version of Vivado are you using and which version of ModelSim?

 

In Vivado 2017.3 and 2017.4, the minimum supported version of ModelSim is 10.6b.

 

If you set simulator to ModelSim in the GUI and run the simulation does ModelSim launch correctly?

 

Best Regards
Aidan

 

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amaccre
Moderator
Moderator
1,749 Views
Registered: ‎04-24-2013

Hi @rmogster,

 

Which version of Vivado are you using and which version of ModelSim?

 

In Vivado 2017.3 and 2017.4, the minimum supported version of ModelSim is 10.6b.

 

If you set simulator to ModelSim in the GUI and run the simulation does ModelSim launch correctly?

 

Best Regards
Aidan

 

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rmogster
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Registered: ‎12-12-2017

The bug was in how I was creating the sim libs.  Got it fixed.  Thanks.

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