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Explorer
Explorer
750 Views
Registered: ‎05-07-2012

Two post implementation FPGA simulation

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Hello,

 

I want to do a  post implementation simulation of a communication link between a couple of Artix FPGAs.  So, I synthesize and implement the HDL design.  It is the same design on both chips.  Then in a behavioral test bench I instantiate this twice, once for each FPGA.  I connect the IO of the two instantiations  and then have one send data to the other.  It isn't working.  Signals that are fine at the test bench level are not right on the top level entities under test.  It is as if both instantiations are linked to the same implementation.  

 

So, does the Vivado simulation tool support what I want to do here?  If so, is there any special setup that I have to do?

 

Thanks.

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Moderator
Moderator
945 Views
Registered: ‎09-15-2016

Re: Two post implementation FPGA simulation

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Hi @sprl111,

 

>> I connect the IO of the two instantiations  and then have one send data to the other.  It isn't working.  

 

Can you please elaborate more on the issue you are facing and please share a test case this will help us understand on what you are trying to achieve.

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
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Moderator
Moderator
946 Views
Registered: ‎09-15-2016

Re: Two post implementation FPGA simulation

Jump to solution

Hi @sprl111,

 

>> I connect the IO of the two instantiations  and then have one send data to the other.  It isn't working.  

 

Can you please elaborate more on the issue you are facing and please share a test case this will help us understand on what you are trying to achieve.

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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