10-16-2016 04:45 PM
The complete message received is:
[USF-XSim 62] 'elaborate' step failed with error(s) while executing 'C:/Xilinx/Projects/Vivado2016_3/Correlator_OOC/Correlator_OOC.sim/sim_1/behav/elaborate.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.
The issue is produced not all the time but lately is becoming permanent when I start Behavioral Simulation. The issue is present using Vivado 2016.2 and also with the new version 2016.3. I am enclosing the following files: compile.log, elaborate.log and xvlog.log. My design is working, I can synthesize, implement and generate bitstream. Even I can program my Nexys4 board. I need to make some changes so the simulation is very important for me in this moment. I will appreciate any comment.
Thanks and regards,
10-16-2016 08:45 PM
1) Try deleting the xsim.dir under your simulation folder.
2) If that doesnt help, try creating a fresh project and see if that helps.
10-16-2016 09:40 PM
10-18-2016 06:55 AM
I tried both options but the problem remains. The issue started working with Vivado 2016.2 and continued creating a fresh project in the new Vivado version 2016.3. I think the problem has to do with Windows. By the way, I am working with Windows 8.1 Pro 64-bits.
10-20-2016 04:40 PM
Do you have any new idea for solving this problem?. I have tried your indication but the problem remains. The simulation (Behavioral Simulation) works once every 10 intents. As you can imagine it is very annoying to work this way. Do you recommend to use ModelSim instead?. I will appreciate any comment about.
07-21-2017 08:08 PM
I am retaken my original post after 9 months now. As everybody can realize I still have the problem and Xilinx has no solution. According to my original post the problem started when I was using 2016.2 VIVADO version. After that I have being using versions 2016.3, 2016.4, 2017.1 and now I am using 2017.2 version and the problem remains. I am sure now that the problem appears regardless the project you are working with; it is something between VIVADO and Windows. By the way, I am using Windows 8.1 Pro 64 bits. The only way to avoid the problem (but it does not work all the time) is restarting the computer. I ask to Xilinx guys, is there any possibility to really solve this problem?; I have tried all the indications you have delivered in the Forum but they do not work. If I not receive any answer I am thinking seriously to move my design to Intel FPGA (former ALTERA).
07-21-2017 08:45 PM
@frivera can you try a different version of windows to see if it makes a difference? windows 10 is significantly better than windows 8.
07-22-2017 09:08 AM
Thanks Teacher for your answer. Unfortunately I do not have the possibility to try a different version of Windows. By the way, I have seen users posts that have reported this problem using different Windows versions like Windows 7. I do not believe that using Windows 10 the problem will be solved. I think it is a serious VIVADO problem that Xilinx should face seriously.