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Registered: ‎05-10-2019

Unable to start behavioural simulation with fixed_pkg

I wish to expand my design with fixed point calculations. I followed instructions in UG901. Currently I only expanded interfaces with sfixed.

 

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use ieee.fixed_pkg.all;


package interface_pkg is
    constant RAM_SIZE: natural:=1024; 
    subtype data_type is signed(11 downto 0);

	type to_mem is record
		RAM_RESET: std_logic;--! Active low, disables RAM
		--EN_OUTPUT: std_logic;
		REN: std_logic;--!Enables read from RAM
		WEN: std_logic;--! Enable write to the RAM
		ADDR: natural range 0 to RAM_SIZE-1;--!Address of the RAM cell
		RE: data_type;--!Input of the real part
		IM: data_type;--!Input of the imaginary part
	end record;
	

	constant DEFAULT_TO_MEM: to_mem:=(RAM_RESET=>'0',
	REN=>'0', WEN=>'0', ADDR=>RAM_SIZE-1, RE=>(others=>'0'),IM=>(others=>'0'));
	

	type from_mem is record 
		RE: data_type;--! Output of the real part
		IM: data_type;--! Output of the imaginary  part
		READY:std_logic;--! Signals that the RAM is switched to a module (active high)
	end record;
	

	constant DEFAULT_FROM_MEM: from_mem:=(RE=>(others=>'0'),IM=>(others=>'0'), READY=>'0');
	
	constant twiddle_fraction: integer:=10;
	
	type complex_sfixed is record
	RE: sfixed;
	IM: sfixed;
	end record;
	
	subtype twiddle_type is complex_sfixed(RE(1 downto -twiddle_fraction), IM(1 downto -twiddle_fraction));
	
end package interface_pkg;			

 

The I can elaborate and synthesize and even run the post-synthesis functional simulation, but not the behavioral one. If I comment out fixed_pkg, complex_sfixed and twiddle_type, I can start it again.

The tcl console

launch_simulation -simset [get_filesets sys_behav_sim ]
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.sim/sys_behav_sim/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sys_behav_sim'
INFO: [SIM-utils-54] Inspecting design source files for 'proc_sys_tb' in fileset 'sys_behav_sim'...
INFO: [SIM-utils-43] Exported '/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.sim/sys_behav_sim/behav/xsim/run.tcl'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sys_behav_sim'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.sim/sys_behav_sim/behav/xsim'
xvhdl --incr --relax -prj proc_sys_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd" into library ieee
ERROR: [VRFC 10-2987] 'std_logic_1164' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:19]
ERROR: [VRFC 10-2987] 'numeric_std' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:20]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:48]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:50]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:339]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:341]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:347]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:349]
ERROR: [VRFC 10-2989] 'signed' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:354]
ERROR: [VRFC 10-2989] 'signed' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:356]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:378]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:379]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:381]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:382]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:383]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:384]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:385]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:386]
ERROR: [VRFC 10-2989] 'std_ulogic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/imports/Vivado/fixed_pkg_2008.vhd:387]
INFO: [#UNDEF] Sorry, too many errors..
INFO: [VRFC 10-163] Analyzing VHDL file "/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd" into library xil_defaultlib
ERROR: [VRFC 10-2987] 'std_logic_1164' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:6]
ERROR: [VRFC 10-2987] 'numeric_std' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:7]
ERROR: [VRFC 10-2987] 'fixed_pkg' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:8]
ERROR: [VRFC 10-2989] 'signed' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:13]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:18]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:20]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:21]
ERROR: [VRFC 10-2989] 'data_type' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:23]
ERROR: [VRFC 10-2989] 'data_type' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:24]
ERROR: [VRFC 10-3562] near character ''0'' ; 2 visible types match here [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:28]
ERROR: [VRFC 10-3562] near character ''0'' ; 2 visible types match here [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:29]
ERROR: [VRFC 10-1478] type of aggregate cannot be determined without context ; 7 visible types match here [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:29]
ERROR: [VRFC 10-2989] 'data_type' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:35]
ERROR: [VRFC 10-2989] 'data_type' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:36]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:37]
ERROR: [VRFC 10-1478] type of aggregate cannot be determined without context ; 8 visible types match here [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:41]
ERROR: [VRFC 10-3562] near character ''0'' ; 2 visible types match here [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:41]
ERROR: [VRFC 10-3782] unit 'interface_pkg' ignored due to previous errors [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd:11]
INFO: [VRFC 10-3070] VHDL file '/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/interface_pkg.vhd' ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd" into library xil_defaultlib
ERROR: [VRFC 10-2987] 'std_logic_1164' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:23]
ERROR: [VRFC 10-2987] 'interface_pkg' is not compiled in library 'xil_defaultlib' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:24]
ERROR: [VRFC 10-2987] 'numeric_std' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:27]
INFO: [VRFC 10-3107] analyzing entity 'test_module'
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:35]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:36]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:37]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:38]
ERROR: [VRFC 10-2989] 'from_mem' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:39]
ERROR: [VRFC 10-2989] 'to_mem' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:40]
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:41]
ERROR: [VRFC 10-3782] unit 'test_module' ignored due to previous errors [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd:34]
INFO: [VRFC 10-3070] VHDL file '/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/test_module.vhd' ignored due to errors
INFO: [VRFC 10-163] Analyzing VHDL file "/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd" into library xil_defaultlib
ERROR: [VRFC 10-2987] 'std_logic_1164' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:23]
ERROR: [VRFC 10-2987] 'interface_pkg' is not compiled in library 'xil_defaultlib' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:24]
ERROR: [VRFC 10-2987] 'numeric_std' is not compiled in library 'ieee' [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:27]
INFO: [VRFC 10-3107] analyzing entity 'memory_access_ctrl'
ERROR: [VRFC 10-2989] 'std_logic' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:35]
ERROR: [VRFC 10-2989] 'std_logic_vector' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:37]
ERROR: [VRFC 10-2989] 'std_logic_vector' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:38]
ERROR: [VRFC 10-2989] 'std_logic_vector' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:39]
ERROR: [VRFC 10-2989] 'to_mem' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:40]
ERROR: [VRFC 10-2989] 'from_mem' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:41]
ERROR: [VRFC 10-2989] 'to_mem' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:42]
ERROR: [VRFC 10-2989] 'from_mem' is not declared [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:43]
ERROR: [VRFC 10-3782] unit 'memory_access_ctrl' ignored due to previous errors [/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd:34]
INFO: [VRFC 10-3070] VHDL file '/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.srcs/sources_1/new/memory_access_ctrl.vhd' ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.sim/sys_behav_sim/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/media/aluzhanskij/1792-47C5/Masterarbeit/Vivado/Processing_System/Processing_System.sim/sys_behav_sim/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

The hierachy:

design_hierarchy.png

 

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4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
566 Views
Registered: ‎07-16-2008

Below is referenced from UG900:

Fixed and floating point packages used by the Vivado simulator are the new enhanced IEEE standard packages introduced in VHDL-2008. If you are using the VHDL-93 standard fixed or floating package, that may work in Vivado synthesis, however you must edit your VHDL source file for simulation.
For example:
If you are using the following syntax for the fixed package in Vivado synthesis:
library ieee;
use ieee.fixed_pkg.all;
Change this to the following syntax in VHDL-2008 for use in the Vivado simulator:
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

-------------------------------------------------------------------------
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Visitor
Visitor
551 Views
Registered: ‎05-10-2019

I find the quotation very confusing. 

Like I mentioned, I followed instructions in UG901, Ch. 6 and directly included Xilinx version of the fixed_package int my design:

"the VHDL-2008 version of fixed-point packages use package instantiation which is not supported in Vivado synthesis; consequently, a
modified version of the fixed_pkg.vhd file is provided in the Vivado...

First, compile the Fixed Package in the IEEE library.
This package is available in the file: fixed_pkg_2008.vhd, in the scripts/rt/data/
directory in your Vivado install.
This package is not precompiled in Vivado, so you must compile the file in your design....

In your VHDL code, you need to add a line to make use of the fixed package (fixed_pkg),
which is provided in the build.

 

library ieee;
use ieee.std_logic_1164;
use ieee.fixed_pkg.all;

 

 

"

Now UG 900 suggests that there is a precompiled version of fixed package after all. And i supposed to have 2 versions: one for simulation with "ieee_proposed" and another with "ieee" for synthesis?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Yes, please try to switch to ieee_proposed library when running simulation.

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Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Visitor
Visitor
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Registered: ‎05-10-2019

Ultimately, this is all futile because the simulator doesn't support uncomstrained types

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