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Anonymous
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Unable to view simulated results

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Hi,

 

    I am using float_pkg from www.eda.org/fphdl. I wrote the following VHDL code to evaluate the following expression just as a beginning step. c=(a*b+a+2)*a where 'a','b' and 'c' are IEEE 754 32 bit floating point data. I am using Xilinx ISE Project Navigator 14.7. In that I am using Isim simulator. Simulation was successful. But all the variables are 'undefined' and no wave form is appearing. I have attached the code, testbench and snapshot of simulator window

 

code:

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.float_pkg.ALL;

entity understand_1 is
       port(a,b: in float32;
	       clk: in std_logic;
		  c: out float32
            );
end entity;

architecture arch of understand_1 is
begin
     process(clk)
	         variable answer1,answer2,answer3,answer4:float32;
		 begin
		
		      if(rising_edge(clk)) then
					  
			answer1:=a*b;
			answer2:=a+to_float(2);
			answer3:=answer1+answer2;
			answer4:=answer3*a;
						  
		      end if;
		      c<=answer4;
    end process;
end architecture;

and test bench is

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.float_pkg.ALL;

entity understand_1_tb is
end entity;

architecture arch of understand_1_tb is
component understand_1
           port(a,b: in float32;
		clk: in std_logic;
		  c: out float32
               );
end component;

signal a,b,c:float32;
signal clk:std_logic;

begin
    uut: understand_1 PORT MAP (a => a,b => b, clk => clk, c =>c );
    process
           begin
               clk <= '0';
	       a<=to_float(2);
	       b<=to_float(1);
               wait for 0.5ns;
               clk <= '1';
               wait for 0.5ns;
end process; end architecture;

 

 

Capture.JPG

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Anonymous
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14,997 Views

Re: Unable to view simulated results

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Hi Aasish,

 

            Thank you for the reply. I actually deleted my previous works. So I can't send the zip file. But after seeing your reply, I created a new project and copied the code from my own above post. This time it worked.

 

 

Thank you

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Highlighted
Xilinx Employee
Xilinx Employee
8,096 Views
Registered: ‎02-14-2014

Re: Unable to view simulated results

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Hello,

 

I have simulated your design with ISE 14.7 on my system and I can see the signals appearing in waveform window with their proper values. I have attached snapshot for your reference.

 

In the snapshot which you have attached, there is an error in the Isim console which mentions that there is mismatch in source and target size. Can you please check if it is really a case?

 

Is it possible to share archived project (Project -> Archive) so that I can reproduce the issue and suggest some workaround. 

Regards,
Ashish
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Anonymous
Not applicable
14,998 Views

Re: Unable to view simulated results

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Hi Aasish,

 

            Thank you for the reply. I actually deleted my previous works. So I can't send the zip file. But after seeing your reply, I created a new project and copied the code from my own above post. This time it worked.

 

 

Thank you

View solution in original post

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