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arrr
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Participant
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Registered: ‎07-19-2018

Using AXI VIP slave mode to imitate mig to debug my custom ip

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This is my testbench for AXI VIP slave mode and its waveform.I have 4 questions about this.

1.I will connect my custom ip to MIG in the future, and I want to verify my custom ip by using AXI VIP in slave mode first. I want to know whether the axi interface of MIG works like this.

2.Why are there 4 clock delays between ARVALID and ARREADY when ARVALID is asserted at the beginning?

3.Why are there 3 clock delays between AWVALID and AWREADY when AWVALID is asserted at the beginning?

4.Why are the clock cycles of the three signals ARREADY, AWREADY, and WREADY three clocks?

I don’t understand the mechanism of axi vip, but I used vivado to build a new axi4 peripheral with an axi slave interface, and I saw the code it generates. According to the code, I think the clock cycle should be only 2 clocks.

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/08/25 12:09:30
// Design Name: 
// Module Name: test2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

import axi_vip_pkg::*;
import design_1_axi_vip_0_1_pkg::*;

module test2(

    );
    
    bit [63:0]C_data_0_0;
    bit [63:0]C_data_1_0;
    bit [63:0]C_data_2_0;
    bit [63:0]C_data_3_0;
    bit C_read_0;
    bit K_read_0;
    bit L_read_0;
    bit OUT_1_0;
    bit [31:0]OUT_addr_0;
    bit [31:0]OUT_data_0;
    bit [299:0]SR_data_0;
    bit SR_read_0;
    bit m00_axi_aclk_0 = 0;
    bit aresetn_0;
    bit [511:0]block_K_0;
    bit [511:0]block_L_0;
    bit m00_axi_aresetn_0;
    bit m00_axi_error_0;
    bit m00_axi_init_axi_txn_0;
    bit m00_axi_txn_done_0;
    bit rc_done_0;
    bit [31:0]read_addr_0;
    bit start_single_read_0;
    bit start_single_write_0;

    design_1_wrapper DUT
    (
        .C_data_0_0(C_data_0_0),
        .C_data_1_0(C_data_1_0),
        .C_data_2_0(C_data_2_0),
        .C_data_3_0(C_data_3_0),
        .C_read_0(C_read_0),
        .K_read_0(K_read_0),
        .L_read_0(L_read_0),
        .OUT_1_0(OUT_1_0),
        .OUT_addr_0(OUT_addr_0),
        .OUT_data_0(OUT_data_0),
        .SR_data_0(SR_data_0),
        .SR_read_0(SR_read_0),
        .m00_axi_aclk_0(m00_axi_aclk_0),
        .aresetn_0(aresetn_0),
        .block_K_0(block_K_0),
        .block_L_0(block_L_0),
        .m00_axi_aresetn_0(m00_axi_aresetn_0),
        .m00_axi_error_0(m00_axi_error_0),
        .m00_axi_init_axi_txn_0(m00_axi_init_axi_txn_0),
        .m00_axi_txn_done_0(m00_axi_txn_done_0),
        .rc_done_0(rc_done_0),
        .read_addr_0(read_addr_0),
        .start_single_read_0(start_single_read_0),
        .start_single_write_0(start_single_write_0)
    );
    
    design_1_axi_vip_0_1_slv_mem_t              agent;
    
    initial begin
 
        m00_axi_aresetn_0 = 1'b0;
        aresetn_0 = 1'b0;
        repeat (16) @(negedge m00_axi_aclk_0);
    
        m00_axi_aresetn_0 = 1'b1;
        aresetn_0 = 1'b1;
    end
    
    initial begin
        
        agent = new("slave vip mem agent",test2.DUT.design_1_i.axi_vip_0.inst.IF);
        agent.set_agent_tag("My Slave VIP");
        
        agent.set_verbosity(0);  
        agent.start_slave();

        start_single_read_0 = 1;
        start_single_write_0 = 1;

    end
    
    always #5ns m00_axi_aclk_0 = ~m00_axi_aclk_0;   
endmodule

question4.PNG

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dgisselq
Scholar
Scholar
618 Views
Registered: ‎05-21-2015

@arrr,

Let me caution you when using this AXI VIP: it's great for demonstrating that your design *can* work, but horrible for proving that your design will work in all cases.  It's known for leaving certain bugs behind, unrevealed.

Looking at the trace below, it looks nothing like how the MIG will interact with a design.  When using the MIG, you can expect a delay of about 20-22 clock cycles from AWVALID and WVALID to BVALID or equivalently from ARVALID to RVALID.  The MIG will also appear to stall randomly at times when it needs to run DRAM refresh cycles.  Further, SDRAMs support reading or writing but never both at the same time, so again expect one of your channels (read or write) to get stalled for a significant time while the other channel is active.  Finally, unlike this VIP you are using below, the MIG is able to retire one beat of transfer per clock.  So, other than the tremendous latency, you should have much better throughput when using it than the VIP is showing you below.

Dan

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3 Replies
dgisselq
Scholar
Scholar
619 Views
Registered: ‎05-21-2015

@arrr,

Let me caution you when using this AXI VIP: it's great for demonstrating that your design *can* work, but horrible for proving that your design will work in all cases.  It's known for leaving certain bugs behind, unrevealed.

Looking at the trace below, it looks nothing like how the MIG will interact with a design.  When using the MIG, you can expect a delay of about 20-22 clock cycles from AWVALID and WVALID to BVALID or equivalently from ARVALID to RVALID.  The MIG will also appear to stall randomly at times when it needs to run DRAM refresh cycles.  Further, SDRAMs support reading or writing but never both at the same time, so again expect one of your channels (read or write) to get stalled for a significant time while the other channel is active.  Finally, unlike this VIP you are using below, the MIG is able to retire one beat of transfer per clock.  So, other than the tremendous latency, you should have much better throughput when using it than the VIP is showing you below.

Dan

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arrr
Participant
Participant
519 Views
Registered: ‎07-19-2018

Thanks for your reply.

Do you mean that if I want to debug my costum IP, it will be better to connect MIG to my costum IP directly and perform SIMULATION than using AXI VIP?

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dgisselq
Scholar
Scholar
512 Views
Registered: ‎05-21-2015

@arrr,

Xilinx's VIP uses simulation.  It suffers from all the problems inherent in simulation.

If you want to debug your custom IP, it'd be better to use formal methods than simulation, yes.

Dan