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Visitor
Visitor
1,190 Views
Registered: ‎03-21-2018

Using modports in Vivado

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I am using SystemVerilog interfaces/modports to simplify module connection logic. Here is a snippet of my source file.

I have an interface (called `axi4lite`) with two modports defined: `master` and `slave`. When I instantiate them into my logic, I have something as follows:

axi4lite axi_master();

Module1 DUT1 (
  .axi_aclk (axi_master.master.axi_aclk)
);

Module2 DUT2 (
  .axi_aclk (axi_master.slave.axi_aclk)
);

Running through simulation, I get the following warnings:

WARNING: [VRFC 10-2681] modport master should not be used in hierarchical reference [/home/antonio/fpga/GlueBoard/src/axi4/example/axi4_csr_example.v:127]

WARNING: [VRFC 10-2681] modport slave should not be used in hierarchical reference [/home/antonio/fpga/GlueBoard/src/axi4/example/axi4_csr_example.v:264]

 

I can't find any documentation for these warnings. Can you please describe what this warning means, and what is the preferred coding style? Are these language features synthesizable?

 

Thanks,

Antonio

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Xilinx Employee
Xilinx Employee
1,164 Views
Registered: ‎05-22-2018

Hi @antoniopug,

I think for modports hierarchical referencing is not supported , as the warning is says. Modports are only used in interface port and virtual interface declarations. They are not used to reference individual interface items.

Please check this AR# for System Verilog support:

https://www.xilinx.com/support/answers/51837.html

Hope the provided information will be helpful.

Regards,

Raj

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Xilinx Employee
Xilinx Employee
1,165 Views
Registered: ‎05-22-2018

Hi @antoniopug,

I think for modports hierarchical referencing is not supported , as the warning is says. Modports are only used in interface port and virtual interface declarations. They are not used to reference individual interface items.

Please check this AR# for System Verilog support:

https://www.xilinx.com/support/answers/51837.html

Hope the provided information will be helpful.

Regards,

Raj

View solution in original post

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Visitor
Visitor
1,144 Views
Registered: ‎03-21-2018

Thanks, using that coding style resolved this issue.

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Xilinx Employee
Xilinx Employee
1,128 Views
Registered: ‎05-22-2018

Hi @antoniopug,

If you query is resoved, please close this thread by marking it as accepted solution. 

Thanks,

Raj.

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