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Registered: ‎11-13-2017

VHDL BEGINNER BASIC DOUBTS

my program is everything is executing but when comes to graphic output it showing zero why

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Registered: ‎09-15-2016

Re: VHDL BEGINNER BASIC DOUBTS

Hi @ravadamadhu245,

 

Make sure you are initializing or forcing values to your design/create test-bench. 'U' should indicate default value.

 

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Registered: ‎01-16-2013

Re: VHDL BEGINNER BASIC DOUBTS

@ravadamadhu245,

 

Write a test bench for your top module. The below link has material for beginners. 

http://www.asic-world.com/verilog/art_testbench_writing.html

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Registered: ‎11-13-2017

Re: VHDL BEGINNER BASIC DOUBTS

i cant understand what u r saying @prathikm. see these files and answer to my questions

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Registered: ‎01-16-2013

Re: VHDL BEGINNER BASIC DOUBTS

@ravadamadhu245,

 

You are trying to use sequential test bench to test combinational circuit which is incorrect. 

Use the below test bench:

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY new_tb IS
END new_tb;

ARCHITECTURE behavior OF new_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT new2
PORT(
switch1 : IN std_logic;
switch2 : IN std_logic;
led1 : OUT std_logic
);
END COMPONENT;

--Inputs
signal switch1 : std_logic := '0';
signal switch2 : std_logic := '0';

--Outputs
signal led1 : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name


BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: new2 PORT MAP (
switch1 => switch1,
switch2 => switch2,
led1 => led1
);

stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

-- insert stimulus here
switch1<='0';
switch2<='0';
wait for 10 ns;
switch1<='1';
switch2<='0';
wait for 10 ns;
switch1<='0';
switch2<='1';
wait for 10 ns;
switch1<='1';
switch2<='1';

wait;
end process;

END;

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Registered: ‎11-13-2017

Re: VHDL BEGINNER BASIC DOUBTS

WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.

WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.

This is a Lite version of ISim.

 

 

like this warnings is coming

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Registered: ‎09-15-2016

Re: VHDL BEGINNER BASIC DOUBTS

Hi @ravadamadhu245

 

Do you see any issue while running simulation except these warnings?

Are you using webpack version of  ISE? If Yes, then it includes lite version of ISIM. You can check the Xilinx configuration manager to verify whether you are using Webpack license. In the ISE GUI, on the top go to Help--> Manage license. This will open the manage license GUI

ISIM is integrated with ISE /Vivado tool and not available in standalone. Nowadays if you buy Vivado system edition license then you will get ISE system edition for free which includes ISIM full version.

Refer the below link:

https://www.xilinx.com/products/design-tools/isim/ise-simulator-faq.html

 

Regards

Rohit

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Regards
Rohit
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