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efrpass
Newbie
Newbie
2,703 Views
Registered: ‎06-10-2017

VHDL Behavioral vs Post-Route

I'm having an issue with my project.

I implemented a counter of rising edges that each 10 shots should give a signal and after other 10 a new one.

Now the behavioral simulation it went well while in the post-rout I've an issue with clock.

Are there any requirements or precaution to be taken for the post-route simulation? How I can handle the clock to have a good result in the post-route too?

Maybe I provide few details but I don't post the code since I hope that the issue is not there.

Thanks in advance

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drjohnsmith
Teacher
Teacher
2,678 Views
Registered: ‎07-09-2009

source code ? 

 

Simulation clock frequency

   simulation resolution 

 

picture of simulation output,

  

basically a bit more information might give us a hand

 

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vijayak
Xilinx Employee
Xilinx Employee
2,631 Views
Registered: ‎10-24-2013

Hi @efrpass

 

Can you provide details on the issue you are seeing? May be the waveform comparison (Behavioral Vs  Post-Route) which shows the expected results.

Check the synthesis and implementation log files to see if any of the logic getting trimmed causing this issue.

Thanks,Vijay
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