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Contributor
Contributor
852 Views
Registered: ‎11-10-2011

VHDL / Vivado Simulation / Vector size are not checked.

Sizes of vectors are not checked in variable assignments.

 

The following code have an error; x(31 DOWNTO 0) := a(15 DOWNTO 0); but Vivado do not detect it.

 

FUNCTION Check(a : STD_LOGIC_VECTOR(15 DOWNTO 0)) RETURN STD_LOGIC_VECTOR IS
   VARIABLE x : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
   x := a;
  RETURN(x);
END FUNCTION Check;
Tags (2)
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9 Replies
Moderator
Moderator
847 Views
Registered: ‎05-31-2017

Re: VHDL / Vivado Simulation / Vector size are not checked.

Hi @walter.gallegos,

 

I have checked a small test case in Vivado 2018.2 and XSIM did give the below error regarding the size mismatch.

ERROR: [VRFC 10-664] expression has 18 elements ; expected 16 

 

Here I have attached the code that I have checked at my end. Please share a test case if you still face the issue.

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Contributor
Contributor
836 Views
Registered: ‎11-10-2011

Re: VHDL / Vivado Simulation / Vector size are not checked.

MOD =>  "Please share a test case if you still face the issue."

 

Read again.

 

"Sizes of vectors are not checked in variable assignments"

 

See the code posted.

 

 

 

 

 

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Moderator
Moderator
819 Views
Registered: ‎03-16-2017

Re: VHDL / Vivado Simulation / Vector size are not checked.

Hi @walter.gallegos,

 

Which Vivado version are you using? 

 

I have checked a small testcase with variable assignments with function with Vivado 2018.2 and it throws an error in elaboration and also in synthesis as well. 

 

 

mismatccc.JPG

 

Regards,

hemangd

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Contributor
Contributor
813 Views
Registered: ‎11-10-2011

Re: VHDL / Vivado Simulation / Vector size are not checked.

I'm using

 

Vivado v2017.4 (64-bit)
  SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
  IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017

 

My test code :

 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Testbench IS
END Testbench;

ARCHITECTURE TB OF Testbench IS
 
SIGNAL a : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL c : STD_LOGIC_VECTOR(31 DOWNTO 0);

FUNCTION Check(a : STD_LOGIC_VECTOR(15 DOWNTO 0)) RETURN STD_LOGIC_VECTOR IS
VARIABLE x : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
  x := a;
RETURN(x);
END FUNCTION Check;
 
BEGIN
 
Stim : PROCESS
BEGIN
  a <= x"1000";
  WAIT FOR 10 ns;
  c <= Check(a);
END PROCESS Stim;

END TB;
 
Simulation script
 
set simu Simu
set work work

exec xvhdl -2008 -work $work $simu/Test.vhd
exec xelab TestBench -debug typical -rangecheck
exec xsim TestBench -gui -view Simu/Test.wcfg
 
Simulation waveform attached.
 
 
 
 

 

 

 

 

Captura de pantalla de 2018-10-08 12-05-07.png
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Contributor
Contributor
804 Views
Registered: ‎11-10-2011

Re: VHDL / Vivado Simulation / Vector size are not checked.

Complementing : Using Vivado GUI, same problem.
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Contributor
Contributor
800 Views
Registered: ‎11-10-2011

Re: VHDL / Vivado Simulation / Vector size are not checked.

Complementing 2 :

[Synth 8-690] width mismatch in assignment; target has 32 bits, source has 16 bits ["/home/daniel/.Xilinx/Vivado/TestVariable/TestVariable.srcs/sources_1/imports/Simu/Test.vhd":32]

Synthesis detect the error in V2017.4 but simu not.
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Contributor
Contributor
790 Views
Registered: ‎11-10-2011

Re: VHDL / Vivado Simulation / Vector size are not checked.

@hemangd
Messages are from Synth. Do you check in simulation ?
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Moderator
Moderator
774 Views
Registered: ‎03-16-2017

Re: VHDL / Vivado Simulation / Vector size are not checked.

Hi @walter.gallegos,

 

Yes, i have checked in simulation. 

 

It's look like xsim limitation or tool issue. I will discuss with the parallel experts and if necessary i will proceed to file a CR (change request) with the factory.

 

As a workaround you may use this synthesis errors as a reference to proceed further in your project. 

 

Regards,

hemangd

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Contributor
Contributor
765 Views
Registered: ‎11-10-2011

Re: VHDL / Vivado Simulation / Vector size are not checked.

Thanks for the answer.

Apologies, from the point of view of an old VHDL user, this issue is a very big black hole that break the safety of VHDL. The fact that factory checks don't detected it do not make me confident with the simulation team.

Unfortunately, the workaround is not practical to be used in projects beyond simple examples; is unproductive for the normal day to day design loops. I need run synthesis and check results before each simulation, a too long cycle.

I will appreciate if you keep me updated.

Regards,
Walter

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