10-08-2018 03:59 AM
Sizes of vectors are not checked in variable assignments.
The following code have an error; x(31 DOWNTO 0) := a(15 DOWNTO 0); but Vivado do not detect it.
10-08-2018 04:14 AM
I have checked a small test case in Vivado 2018.2 and XSIM did give the below error regarding the size mismatch.
ERROR: [VRFC 10-664] expression has 18 elements ; expected 16
Here I have attached the code that I have checked at my end. Please share a test case if you still face the issue.
10-08-2018 04:40 AM
MOD => "Please share a test case if you still face the issue."
"Sizes of vectors are not checked in variable assignments"
See the code posted.
10-08-2018 07:06 AM
Which Vivado version are you using?
I have checked a small testcase with variable assignments with function with Vivado 2018.2 and it throws an error in elaboration and also in synthesis as well.
10-08-2018 07:58 AM - edited 10-08-2018 08:14 AM
Vivado v2017.4 (64-bit)
SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
My test code :
10-08-2018 08:59 AM
10-09-2018 12:28 AM
Yes, i have checked in simulation.
It's look like xsim limitation or tool issue. I will discuss with the parallel experts and if necessary i will proceed to file a CR (change request) with the factory.
As a workaround you may use this synthesis errors as a reference to proceed further in your project.
10-09-2018 03:44 AM - edited 10-09-2018 03:49 AM
Thanks for the answer.
Apologies, from the point of view of an old VHDL user, this issue is a very big black hole that break the safety of VHDL. The fact that factory checks don't detected it do not make me confident with the simulation team.
Unfortunately, the workaround is not practical to be used in projects beyond simple examples; is unproductive for the normal day to day design loops. I need run synthesis and check results before each simulation, a too long cycle.
I will appreciate if you keep me updated.