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Adventurer
Adventurer
2,362 Views
Registered: ‎11-08-2017

[VHDL] alias usage for referencing of the hierarchical signals

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Hi All,

 

I'm receiving the following error message while my VHDL code compilation (actually the compilation has passed, this error appears during load_design):

[CODE]
# ** Warning: (vsim-8523) Cannot reference the signal "/tb_bit_mgr_wrp/i_bit_mgr_wrp/i_bit_mgr/i_filter/gen_flt(0)/gen_flr_cnt/i_flr_cnt/flr_cnt" before it has been elaborated.
# Time: 0 ps Iteration: 0 Instance: /tb_bit_mgr_wrp/i_bit_mgr_wrp File: D:/units/bit/rtl/inst/bit_mgr_wrp.vhd
[/CODE]

 

Here is an alias, which I used in my code:
[CODE]alias flr_cnt0_al is <<signal .tb_bit_mgr_wrp.i_bit_mgr_wrp.i_bit_mgr.i_filter.gen_flt(0).gen_flr_cnt.i_flr_cnt.flr_cnt : integer range 0 to FLR_CNT_TRSH>>;[/CODE]

 

What's the problem? The simulator "complains" that it cannot reference the signal before it has been elaborated. How to solve? How to elaborate the signal(s) in this case?

 

Thank you!

 

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1 Solution

Accepted Solutions
Scholar richardhead
Scholar
2,813 Views
Registered: ‎08-01-2012

Re: [VHDL] alias usage for referencing of the hierarchical signals

Jump to solution

"But, the declaration area for the signals/alias in the current architecture is before the place where other entities (sub-hierarchies) are instantiated in the same architecture. So, the only way to declare the alias is inside of some process after all these instances. But, on another hand, an alias, which was declared inside of the process, visible inside of this process only..."

 

All you need to do it put the entity declarations BEFORE the process. The order here should make no difference to functionality, you just need to re-structure the files to make the heirarchy visible to the process.

 

inst : entity work.some_ent
....

process
  alias some_internal_sig is << signal inst.sig : std_logic >>;
begin
...
end

You cannot make external names or aliases like this global, as that would be against the point of external names.

If you really want something global, then declare the signal inside a package.

 

package some_package is
  signal global_sig : std_logic;
end packcage;

....

use work.some_package.all;

architecture arch of some_ent is
  signal a : std_logic;
begin

  a <= global_sig;

end architecture;

Remember though, its still a signal, so must follow the same rules - only drive it from a single process to avoid multiple drivers.

Another caveat - only use these for simulation, not all synthesis tools support global signals.

5 Replies
Scholar richardhead
Scholar
2,317 Views
Registered: ‎08-01-2012

Re: [VHDL] alias usage for referencing of the hierarchical signals

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If you're trying to access an external named object inside an entity, you cannot declare an alias to it until after the entity has been instantiated. Aliases can be declared anywhere, even inside processes, so it is easiest if you just declare it in a process after the entity instantiation.

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Adventurer
Adventurer
2,261 Views
Registered: ‎11-08-2017

Re: [VHDL] alias usage for referencing of the hierarchical signals

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Hm... How can I declare an alias or a signal or a variable inside of the process?

 

Could you please provide an example?

 

What's scope of the signal, which is declared inside of the process? Will the scope be the process itself only or the whole hierarchy level where the process is instantiated?

 

Thank you 

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Scholar richardhead
Scholar
2,240 Views
Registered: ‎08-01-2012

Re: [VHDL] alias usage for referencing of the hierarchical signals

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The scoping rules for alias is the same as anything else - it is local to where it is declared. So an alias declared inside a process is only available inside the process.

 

And alias to a signal can be declared in a process like this :

 

process 
  alias sig_alias : std_logic is some_signal;
begin
  sig_alias <= '1';

 --sig_alias can only be used inside the process;
end process

aliasing to an external name can be used in the same way (with the modification to alias declaration).

 

 

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Adventurer
Adventurer
2,231 Views
Registered: ‎11-08-2017

Re: [VHDL] alias usage for referencing of the hierarchical signals

Jump to solution

"aliasing to an external name can be used in the same way (with the modification to alias declaration)" - OK, but how could it help? How can I define an alias, so that it will be visible to the whole hierarchy? 

 

As I described previously above, I want to refer (alias) to a signal, which is declared inside of another hierarchy/entity. The issue is so that I cannot refer/alias to this signal before the entity (where this signal is declared) is instantiated.

 

But, the declaration area for the signals/alias in the current architecture is before the place where other entities (sub-hierarchies) are instantiated in the same architecture. So, the only way to declare the alias is inside of some process after all these instances. But, on another hand, an alias, which was declared inside of the process, visible inside of this process only...

 

So, how to alias to the signals in other hierarchies and how to make these aliases global?

 

BTW, could a usage in the packets of the signals help? Probably it's better to declare the aliases and signals in the packets?

 

Thank you!

0 Kudos
Scholar richardhead
Scholar
2,814 Views
Registered: ‎08-01-2012

Re: [VHDL] alias usage for referencing of the hierarchical signals

Jump to solution

"But, the declaration area for the signals/alias in the current architecture is before the place where other entities (sub-hierarchies) are instantiated in the same architecture. So, the only way to declare the alias is inside of some process after all these instances. But, on another hand, an alias, which was declared inside of the process, visible inside of this process only..."

 

All you need to do it put the entity declarations BEFORE the process. The order here should make no difference to functionality, you just need to re-structure the files to make the heirarchy visible to the process.

 

inst : entity work.some_ent
....

process
  alias some_internal_sig is << signal inst.sig : std_logic >>;
begin
...
end

You cannot make external names or aliases like this global, as that would be against the point of external names.

If you really want something global, then declare the signal inside a package.

 

package some_package is
  signal global_sig : std_logic;
end packcage;

....

use work.some_package.all;

architecture arch of some_ent is
  signal a : std_logic;
begin

  a <= global_sig;

end architecture;

Remember though, its still a signal, so must follow the same rules - only drive it from a single process to avoid multiple drivers.

Another caveat - only use these for simulation, not all synthesis tools support global signals.