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Explorer
Explorer
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Registered: ‎09-05-2015

VHDL testbench's stimuli convention?

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Hi, I am famailiar with verilog and new to vhdl.

 

I recently purchased a third party's solution that includes vhdl design files and vhdl testbench.

vhdl_sim.PNG

The snapshot above shows my simulation files.

In tb_fmc216.vhd, it has module instantiation and clock generation. But I don't see how input.txt is read from the testbench.

I wonder if there's some convention in vhdl testbench that reads input.txt and generates output.txt.

 

Thanks in advance.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: VHDL testbench's stimuli convention?

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without seeing the files, my crystal ball is in overtime

Its common for test benches to read stimuli,
that way many tests can be run using one test bench,


this shows such an example

https://www.nandland.com/vhdl/examples/example-file-io.html
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Teacher
Teacher
207 Views
Registered: ‎07-09-2009

Re: VHDL testbench's stimuli convention?

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without seeing the files, my crystal ball is in overtime

Its common for test benches to read stimuli,
that way many tests can be run using one test bench,


this shows such an example

https://www.nandland.com/vhdl/examples/example-file-io.html
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Moderator
Moderator
181 Views
Registered: ‎04-24-2013

Re: VHDL testbench's stimuli convention?

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Hi @moon5756 ,

I am not clear on the exact question here, as input.txt has been added to the project files it will be available to the testbench if it is referenced.

If you are using a scripted flow you will either have to include it in the same directory or provide the path to the text file.

Best Regards
Aidan

 

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