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Verilog-Testbench - question

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Adventurer
Posts: 93
Registered: ‎11-22-2016
Accepted Solution

Verilog-Testbench - question

Hello,

I have a clock signal, and in my test bench my intention is to make a reset signal low at the negative edge of clock until that time reset signal needs to be at 1.

 

so I declared a reset signal  and intialized to 1.

reg reset = 1'b1;

 

clock frequency is 390 MHZ, and I am doing the following for clock. I declare reg clock = 1'b1;

 

 

always
 begin
#1282 clock = ~ clock;    //390 MHz.

end

 

now when I want to make that signal low at the neg edge of clock, I call an initial block that does the following

initial begin
reset= 1'b1;
@(negedge clock)  // line 3
reset = 1'b0;
end

 

But I guess this setup forms a loop or something and it would never end, the simulation keeps on running and my .vcd file gets bigger and bigger. SO I don't get any output. 

 

lets say in the above code if I change my line 3 to any delay less than #1000, then the simulation works. couldn't understand where I am going wrong. 

 

Can anyone help me out?

 

Thanks,

Manoj


Accepted Solutions
Adventurer
Posts: 93
Registered: ‎11-22-2016

Re: Verilog-Testbench - question

Thanks for your reply @sunilku and @richardhead.

 

I did have the $finish inside a separate initial block in my code. I guess synopsys VCS tools doesn't allow you to see the waveform if your design/tb is sometimes stuck due to a major logical error, unlike xilinx it will show the wrong waveform which will help us debug more fast.

 

I made a mistake in my tb with reference to Reset and first state jump. So the simulation files won't even gets generated, even after compiling it right. I am new to using Synopsys tools. Used to work with xilinx simulator.

Regards,

Manoj

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All Replies
Xilinx Employee
Posts: 91
Registered: ‎08-10-2015

Re: Verilog-Testbench - question

Hi @manoj_xilinx,

 

You have declared a free running clock and there is no $finish in your test bench code. So Simulation will never end. 

 

Please add $finish after some time period like below 

 

Initial 

     #10000ns $finish;

 

 

Thanks,

Sunilkumar

 

 

Voyager
Posts: 331
Registered: ‎08-01-2012

Re: Verilog-Testbench - question

What kind of reset is it supposed to be? In the code you posted, the clock starts at 1'b1, and so the first event on it is a negedge. So the reset is not held high for any posedge, so anything with a sync reset will not get reset.
Adventurer
Posts: 93
Registered: ‎11-22-2016

Re: Verilog-Testbench - question

Thanks for your reply @sunilku and @richardhead.

 

I did have the $finish inside a separate initial block in my code. I guess synopsys VCS tools doesn't allow you to see the waveform if your design/tb is sometimes stuck due to a major logical error, unlike xilinx it will show the wrong waveform which will help us debug more fast.

 

I made a mistake in my tb with reference to Reset and first state jump. So the simulation files won't even gets generated, even after compiling it right. I am new to using Synopsys tools. Used to work with xilinx simulator.

Regards,

Manoj