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Registered: ‎12-15-2014

Vidado-generate SDF causing errors in ModelSim

I am attempting to run a timing simulation on a very simple design just for the purposes of coming up to speed with Vivado.  At this point I am stuck.  Vivado generates the usual .v and .sdf files for the simulation model.  I pull these into my simulation folder and make it through compiling the various source files.  I figured out how to generate the simprims_ver library from usisims.  ModelSim now makes it all the way up to loading the SDF and then emits the following error:


# SDF 10.1b Compiler 2012.04 Apr 27 2012
# ** Error: top_fpga_a_time_impl.sdf(682): near "|":syntax error, unexpected '|', expecting ')'


The offending line from the SDF is:


(INSTANCE capim_0|capim_aktiv\[0\]_i_1)


Vivado appears to be using the vertical bar as the hierarchy separator and ModelSim expects something else.  I walking through the long modelsim.ini files that Vivado puts in the same folder and the model.  The closest thing I could find to a hierarchy separator is the following:


; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /

  Since I can find no other instance on the Xilinx website regarding this problem with the SDF I have to assume that I am unique in encoutering it.  I learned that this same problem exists in Vivado 2013.4 and 2014.4.  If anyone has figured out how to get past it please let me know.

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Registered: ‎12-15-2014

I found this in a document describing the format of the SDF.

The hierarchy_divider can only be one of two characters.



The hierarchy divider entry specifies which of the two permissible
characters are used in the file to separate elements of a hierarchical path.
hierarchy_divider ::= ( DIVIDER HCHAR )
HCHAR is either a period (.), or a slash (/). It should not be in quotes.
. . .
(INSTANCE a/b/c)
. . .
In this example, the hierarchy divider is specified to be the slash (/)
character and hierarchical paths use / (rather than .) to separate elements.
If the SDF file does not contain a hierarchy divider entry then the default
hierarchy divider is the period (.). See also the descriptions of
IDENTIFIER and PATH in “Syntax Conventions” on page 4-2.

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Registered: ‎12-15-2014

OK.  I opened the SDF and replaced all instances of the vertical bar "|" with a "/".  There were 4600 replacements in my little design.  This eliminated the error that ModelSim was generating.

This is not the correct way to fix this problem but it will do for now.

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Xilinx Employee
Xilinx Employee
Registered: ‎01-04-2013

Can you see if the set_hierarchy_separator command has been used to set the '|' character? You can use get_hierarchy_separator to get the current defined value.


You can set the hierarchy separator to '/' using the following command:

set_hierarchy_separator /





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