UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor tonywu2000
Visitor
5,546 Views
Registered: ‎04-29-2014

Vivado 2014.1 Modelsim simulation for Microblaze

I have been struggling to make the Microblaze simulation work for one week now. I basically just make a very simple Microblaze block with UART & one GPO. I expect to see the GPO and UART tx toggling but the microblaze doesn't seem to run. I am sure the simulation is working becuase I add a counter  and I can see the output counting.

 

I then take a look at the "top_time_impl.v" file and it is supposed to load the "design_1_lmb_bram_0.mem" file. Following is the text I found:

 

(* CORE_GENERATION_INFO = "design_1_lmb_bram_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VERILOG,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=design_1_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=8192,C_READ_DEPTH_A=8192,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=8192,C_READ_DEPTH_B=8192,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}" *)
module design_1_lmb_bram_0

.....

 

I am not sure what is the syntac (* .... *). Is it a comment or it really loads the *.mem file here? I try to delete the *.mem file and the simulation still runs. Strange?

 

I upload the "top_time_impl.v"  & "design_1_lmb_bram_0.mem" files. Could someone please help me with this issue?  

 

Thanks

 

Tony

0 Kudos
1 Reply
Moderator
Moderator
5,502 Views
Registered: ‎04-17-2011

Re: Vivado 2014.1 Modelsim simulation for Microblaze

The comment specifies the coregen options. The .mem is used while running simulation.
There is a mcs_sim.pdf file suggested in one of the http://forums.xilinx.com/t5/Embedded-Development-Tools/MicroBlaze-MCS-simulation-with-ISim/td-p/395099 which you can cross check to see if the simulation is setup properly. It is for ISIM but would equally hold good for Modelsim.
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos