UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mkachalov1
Visitor
9,698 Views
Registered: ‎03-16-2015

Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

Hello,

 

I am using Vivado 2014.4 and generated a SRIO Gen2 v3.2 core. My goal is to use this core to generate SRIO traffic.

 

I used the forum answer record below to generate the example design:

https://forums.xilinx.com/t5/Networking-and-Connectivity/Vivado-2014-3-SRIO-Gen2-v3-2-example-does-not-get-generated/m-p/554961#M7144

 

Once I have the example design, I am trying to simulate it in Modelsim. One of the blocks that is instantiated is "srio_gen2_v3_2_unifiedtop" (see attatchment), however, I don't think this was an output of Vivado 2014.4 when I generated the example design.

 

Any help would be appreciated,

Michael

 

 

 

 

Tags (1)
srio_gen2_v3_2_unifiedtop.PNG
0 Kudos
7 Replies
Xilinx Employee
Xilinx Employee
9,650 Views
Registered: ‎02-06-2013

Re: Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

Hi 

 

Srio_gen2_v3.2_unifiedtop is the instantiation of the encrypted core file generated as output and the encrypted file can be seen at below hierarchy but name

 

......example.srcs\sources_1\ip\srio_gen2_0\srio_gen2_v4_0_2\hdl

 

Do you face any issue's while running simulation of the example design?

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Visitor mkachalov1
Visitor
9,607 Views
Registered: ‎03-16-2015

Re: Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

Hello,

 

It looks like you are using gen2 version 4.0 while I am still on gen2 version 3.2, I don' tthink this should matter?

 

To make sure we are on the same page, I followed the path posted, are these the files you are refferring to?

 

Thanks

srio_gen2_v3_2_snap.PNG
0 Kudos
Xilinx Employee
Xilinx Employee
9,575 Views
Registered: ‎02-06-2013

Re: Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

Hi

 

Yes those are the encrypted files i am referring to.

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Highlighted
Visitor mkachalov1
Visitor
9,527 Views
Registered: ‎03-16-2015

Re: Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

HeY Satish,

 

I compiled both of the files into my Modelsim work directory. When I try to simulate the example design as described by PG007 Gen2 v3.2 (October 1, 2014) page 155, I get the following error:

** Error: nofile(53): in protected region

 

I know this is related to the srio_gen2_v3_2_rfs.vhd and srio_gen2_v3_2_rfs.v files because when I create a new project without those two files I get the error below

 

Module 'srio_gen2_v3_2_unifiedtop' is not defined.

 

Do you know what this nofile in protected region can mean?

error_nofile.PNG
0 Kudos
Xilinx Employee
Xilinx Employee
9,511 Views
Registered: ‎02-06-2013

Re: Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

Hi

 

Make sure you are using compatible Modelsim version and compiled the libraries correctly(Refer UG900).

 

Also refer below related thread

https://forums.xilinx.com/t5/Simulation-and-Verification/SRIO-Gen2-netlist-models-slow-behavioral-models-encrypted/td-p/431110

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Visitor mkachalov1
Visitor
9,475 Views
Registered: ‎03-16-2015

Re: Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

Hey Satish,

 

I have the necessary Xilinx libraries. I went to Vivado -> Tools -> Compile Simulation Libraries.. -> Compile; and made sure to point to the pre compiled libraries in my Modelsim.ini file.

 

Per the forum you linked:

https://forums.xilinx.com/t5/Simulation-and-Verification/SRIO-Gen2-netlist-models-slow-behavioral-models-encrypted/td-p/431110

 

There was a note "The library name MUST be unchanged. Else you get an error and because the file is encrypted, this was really painful to find out... Xilinx IP core models being dependant to their library name is definitely NOT a good practice in my opinion..."

 

As I understand it, I need to compile the srio_gen2_v3_2_rfs.v and srio_gen2_v3_2_rfs.vhd into a "srio_gen2_v3_2_unifiedtop" library. I have the following two commands:

 

vcom -novopt -work srio_gen2_v3_2_unifiedtop \
       <path>/srio_gen2_v3_2_rfs.vhd

vlog -novopt -incr -work srio_gen2_v3_2_unifiedtop \
       <path>/srio_gen2_v3_2_rfs.v

 

However, they do not seem to do anything as the generated library is empty (see attachment). When I try to simulate, I get a "Module 'srio_gen2_v3_2_unifiedtop' is not defined.: error.

 

In my previous post, I compiled those two files into my work library and got a "** Error: nofile(53): in protected region" error.

 

Any thoughts?

Thanks

srio_library_empty.PNG
0 Kudos
Xilinx Employee
Xilinx Employee
9,455 Views
Registered: ‎02-06-2013

Re: Vivado 2014.4 - srio_gen2_v3-2_unifiedtop

Hi

 

I suggest to do integrated Modelsim simulation and see if you face any issue's with it or if using standalone mode then use the scripts only option to genrate the simulaiton scripts which will take care of the library mapping and file fetching needed for the simulation.

 

Refer below doc for the command options to generate simulation scripts

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos