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dsag
Newbie
Newbie
7,688 Views
Registered: ‎05-24-2016

Vivado 2015.4 Simulation generates incorrect paths to IP on Windows path with space.

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Hi all,

 

We have been trying to run a verilog simulation with Vivado 2015.4 on Windows 7, and have discovered that if the local path has a space in it, the vivado_prj.sim\sim_1\behav\testbench_vlog.prj file generated by Vivado has mistakes in the paths to the IP paths that are included.

 

The exact same simulation (RTL, testbench code, TCL scripts etc) works fine on Vivado 2014.4.

 

The simulation also works if the Windows path does not have any spaces in it.

 

Does anyone know if there's any workaround we could introduce into our TCL scripts? Has this issue been resolved in 2016.1? We are aware that the layout of the IP paths changed between 2014.4 and 2015.4, but this seems to have introduced this issue as well.


An example line from testbench_vlog.prj in Vivado 2014.4:

verilog axi_clock_converter_v2_1  "../../../vivado_prj.srcs/sources_1/ip/ip_axi_cconv/axi_clock_converter_v2_1/hdl/verilog/axi_clock_converter_v2_1_axic_sync_clock_converter.v" -i "../../../../verif/tb" -i "../../../../verif/test" -i "../../../../rtl" --include "../../../../rtl" --include "../../../vivado_prj.srcs/sources_1/ip/ip_axi_128to32/axi_infrastructure_v1_1/hdl/verilog" --include "../../../vivado_prj.srcs/sources_1/ip/ip_axi_crossbar/axi_infrastructure_v1_1/hdl/verilog" --include "../../../vivado_prj.srcs/sources_1/ip/ip_axi_ep_xbar/axi_infrastructure_v1_1/hdl/verilog" -d "SIMULATION=1"

And the equivalent line from testbench_vlog.prj in Vivado 2015.4

verilog axi_clock_converter_v2_1_6  "../../../vivado_prj.ip_user_files/ipstatic/axi_clock_converter_v2_1_6/hdl/verilog/axi_clock_converter_v2_1_axic_sync_clock_converter.v" -i "../../../../verif/tb" -i "../../../../verif/test" -i "../../../../rtl" --include "../../../../rtl" --include "../../../vivado_prj.ip_user_files/ipstatic/dsag/Documents/Vivado Simulation/fpga_rtl/prj/vivado_prj.srcs/sources_1/ip/ip_axi_128to32/axi_infrastructure_v1_1_0/hdl/verilog" --include "../../../vivado_prj.ip_user_files/ipstatic/dsag/Documents/Vivado Simulation/fpga_rtl/prj/vivado_prj.srcs/sources_1/ip/ip_axi_crossbar/axi_infrastructure_v1_1_0/hdl/verilog" --include "../../../vivado_prj.ip_user_files/ipstatic/dsag/Documents/Vivado Simulation/fpga_rtl/prj/vivado_prj.srcs/sources_1/ip/ip_axi_ep_xbar/axi_infrastructure_v1_1_0/hdl/verilog" -d "SIMULATION=1"


For both, I am running from within C:\Users\dsag\Documents\Vivado Simulation\fpga_rtl

 

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dsag
Newbie
Newbie
13,972 Views
Registered: ‎05-24-2016

Thank you. I acknowledge that this is a known limitation of Xilinx Vivado 2015.4 and will hopefully be fixed in future releases.

View solution in original post

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3 Replies
dsag
Newbie
Newbie
7,685 Views
Registered: ‎05-24-2016
I meant to also say: You can see that in the 2015.4 example, part of my path has been inserted within the include options; whereas in the 2014.4 case, only relative paths within the vivado project directory appear.
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srimaye
Xilinx Employee
Xilinx Employee
7,665 Views
Registered: ‎09-25-2014

Hi @dsag ,

 

This is an issue and has been reported to factory. As a workaround  , you can change the directory Vivado Simulation\fpga_rtl to Vivado_Simulation\fpga_rtl  to avoid the incorrect paths .

 

Thanks,

Srimayee

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dsag
Newbie
Newbie
13,973 Views
Registered: ‎05-24-2016

Thank you. I acknowledge that this is a known limitation of Xilinx Vivado 2015.4 and will hopefully be fixed in future releases.

View solution in original post

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