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Newbie chuletronix
Newbie
106 Views
Registered: ‎04-17-2013

Vivado 2016.3 ERROR: [XSIM 43-3311] Signal EXCEPTION_STACK_OVERFLOW received

I am working on the integration of several subsystems in a single top system. The HDL of some of these subsystems is available and others only have their synthesis design checkpoint files. The device used is a Virtex7 (VC707).

When trying to perform post-synthesis functional simulation with the XSIM tool, I receive the following error message:

ERROR: [XSIM 43-3311] Signal EXCEPTION_STACK_OVERFLOW received.

I searched the forum and did not find any reference to this error, could you please tell me what could be the cause of this error?

The system that I try to simulate has been synthesized and implemented without errors and satisfying the time constraints.

Attached find the simulator output file (elaborate.log).

The development environment is a computer with a Core i7, 32 GB,  SSD and HDD, and Windows 10.

 

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4 Replies
Moderator
Moderator
74 Views
Registered: ‎05-31-2017

Re: Vivado 2016.3 ERROR: [XSIM 43-3311] Signal EXCEPTION_STACK_OVERFLOW received

Hi @chuletronix,

Can you please once check the same design in the latest Vivado release (2018.3) and if the issue still persists in latest vivado release too then please share us the archived project to debug this issue further.

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Newbie chuletronix
Newbie
61 Views
Registered: ‎04-17-2013

Re: Vivado 2016.3 ERROR: [XSIM 43-3311] Signal EXCEPTION_STACK_OVERFLOW received

Hi @shameera, thanks for your answer.

I have checked my design with Vivado 2018.2 and the issue has disappeared. However, other research groups participating in the project do not have this version of Vidado and therefore I would like to know if there is any other solution to this issue using Vivado 2016.3.

Regards,

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Moderator
Moderator
51 Views
Registered: ‎05-31-2017

Re: Vivado 2016.3 ERROR: [XSIM 43-3311] Signal EXCEPTION_STACK_OVERFLOW received

Hi @chuletronix,

It might be some memory issue with the older vivado version. As you are willing to stick to vivado 2016.3, you need to check for which part of HDL code this error occurs by commenting some part of HDL, simulating and repeating the same till the root cause is found. Once the root cause is found I think we can overcome this error by making some HDL modifications.

Ideally, it is suggested to use the latest vivado tool versions.

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Newbie chuletronix
Newbie
28 Views
Registered: ‎04-17-2013

Re: Vivado 2016.3 ERROR: [XSIM 43-3311] Signal EXCEPTION_STACK_OVERFLOW received

Hi @shameera,

For a big project, which is made up of several subsystems, its solution to comment on code and to advance to trial and error seems not viable. Keep in mind that it is necessary to perform a post-synthesized simulation.
Thank you very much for your response.

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