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Adventurer
Adventurer
1,360 Views
Registered: ‎08-28-2017

Vivado 2017.4 FATAL ERROR SIMULATION KERNEL

Hi,

 

I am working on a simulation of my company's JPEG CORE IP using the Xilinx AXI stream VIP. I am using vivado 2017.4. During the simulation I receive a FATAL error

 

FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 2145482098 ps  Iteration: 0  Process: /axi4stream_vip_pkg/axi4stream_monitor(C_XIL_AXI4STREAM_SIGNAL_SET=8'b10010011,C_XIL_AXI4STREAM_DEST_WIDTH=0,C_XIL_AXI4STREAM_DATA_WIDTH=24,C_XIL_AXI4STREAM_ID_WIDTH=0,C_XIL_AXI4STREAM_USER_WIDTH=1,C_XIL_AXI4STREAM_HAS_ARESETN=1)::watch_and_write/WRITE_TRANS
  File: /wrk/2017.4/nightly/2017_12_15_2086221/prep/rdi/vivado/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv

 

Any Inputs? is this a tool issue?

 

 

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3 Replies
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Moderator
Moderator
1,335 Views
Registered: ‎05-31-2017

Re: Vivado 2017.4 FATAL ERROR SIMULATION KERNEL

Hi @skaat27,

 

Can you once go through the AR#70609 and check if it helps.

Also, I would suggest you to check the same design in latest vivado version (2018.2) and if you see the same FATAL ERROR in 2018.2 too then please share a test case reproducing the issue.

 

Thanks & Regards,
A.Shameer

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Adventurer
Adventurer
1,293 Views
Registered: ‎08-28-2017

Re: Vivado 2017.4 FATAL ERROR SIMULATION KERNEL

Hi @shameera

 

I tried with vivado 2018.2 and still get the same error

 

FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 1905686080 ps  Iteration: 0  Process: /axi4stream_vip_pkg/axi4stream_monitor(C_XIL_AXI4STREAM_SIGNAL_SET=8'b10010011,C_XIL_AXI4STREAM_DEST_WIDTH=0,C_XIL_AXI4STREAM_DATA_WIDTH=24,C_XIL_AXI4STREAM_ID_WIDTH=0,C_XIL_AXI4STREAM_USER_WIDTH=1,C_XIL_AXI4STREAM_HAS_ARESETN=1)::watch_and_write/WRITE_TRANS
  File: /wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv

HDL Line: /wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv:917
WARNING: [Simulator 45-29] Cannot open source file /wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv: file does not exist.

 

This was a perfectly working fine testbench with the AXI BFM MASTER IP. The only difference here is that i use the AXI stream MASTER VIP.

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Xilinx Employee
Xilinx Employee
1,283 Views
Registered: ‎08-10-2015

Re: Vivado 2017.4 FATAL ERROR SIMULATION KERNEL

Hi @skaat27,

 

 

Could you please share the design files ?

 

 

Thanks,

Sunilkumar

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