UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Anonymous
Not applicable
431 Views

Vivado 2018.1 Linux 64 bit Modelsim DE 32 bit - GUI not launching after simulation

Hi All,

I've followed the forums and documentation to get modelsim correctly compiling in my Vivado setup. Everything looks fine, the only issue I have, is that the modelsim GUI never launches at the end of it all. Here is my TCL output from running simulation (NOTE: I also opened some random example project which had a testbench already in it, ran it, same deal, compiles fine but after "Process Launched" nothing ever comes to be). Also, when I launch VSIM from terminal, my Modelsim opens fine (I just don't want to have to go and define all of this stuff manually at this stage and prefer Vivado to do the work as it's designed to).

At present, I have selected "All signals" and am not providing any custom .do files. Any hints appreciated as I'm expecting the modelsim GUI to open up somewhere and all of my signals to be available. My test bench at present is very simple. I've set Vivado up for 32 bit simulation and can confirm modelsim libraries are all compiled against 32 bit and setup correctly.

 

launch_simulation -install_path /opt/modelsim_dlx/bin
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'ModelSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/sf_bmd_repo/Cintel_master/ScannerGen2/UniversalAmp/UniversalAmpVivadoBlock/UniversalAmpVivadoBlock.sim/sim_1/behav/modelsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-ModelSim-47] Finding simulator installation...
INFO: [USF-ModelSim-50] Using simulator executables from '/opt/modelsim_dlx/bin/vsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-modelsim-7] Finding pre-compiled libraries...
INFO: [USF-modelsim-11] File '/home/build/modelsim_libs/modelsim.ini' copied to run dir:'/media/sf_bmd_repo/Cintel_master/ScannerGen2/UniversalAmp/UniversalAmpVivadoBlock/UniversalAmpVivadoBlock.sim/sim_1/behav/modelsim'
INFO: [SIM-utils-54] Inspecting design source files for 'UniversalAmplifier_tb' in fileset 'sim_1'...
INFO: [USF-ModelSim-107] Finding global include files...
INFO: [USF-ModelSim-108] Finding include directories and verilog header directory paths...
INFO: [USF-ModelSim-110] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-ModelSim-111] Fetching design files from 'sim_1'...
INFO: [USF-ModelSim-2] ModelSim::Compile design
INFO: [USF-ModelSim-15] Creating automatic 'do' files...
INFO: [USF-ModelSim-69] Executing 'COMPILE and ANALYZE' step in '/media/sf_bmd_repo/Cintel_master/ScannerGen2/UniversalAmp/UniversalAmpVivadoBlock/UniversalAmpVivadoBlock.sim/sim_1/behav/modelsim'
Model Technology ModelSim DE vmap 10.6b Lib Mapping Utility 2017.05 May 25 2017
vmap xilinx_vip modelsim_lib/msim/xilinx_vip
Modifying modelsim.ini
Model Technology ModelSim DE vmap 10.6b Lib Mapping Utility 2017.05 May 25 2017
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
Modifying modelsim.ini
Model Technology ModelSim DE vlog 10.6b Compiler 2017.05 May 25 2017
Start time: 17:25:19 on Jun 07,2019
vlog -32 -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_2 -L axi_vip_v1_1_2 -L processing_system7_vip_v1_0_4 -L xilinx_vip -work xilinx_vip "+incdir+/opt/Xilinx/Vivado/2018.1/data/xilinx_vip/include" /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi_vip_pkg.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi_vip_if.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/clk_vip_if.sv /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/rst_vip_if.sv
-- Compiling interface axi4stream_vip_axi4streampc
-- Compiling interface axi_vip_axi4pc
-- Compiling package xil_common_vip_pkg
-- Compiling package axi4stream_vip_pkg
-- Importing package xil_common_vip_pkg
** Warning: /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv(1790): (vlog-2254) SystemVerilog testbench feature
(randomization or coverage) detected in the design.
These features are only supported in Questasim.
** Warning: /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv(3044): (vlog-2254) SystemVerilog testbench feature
(randomization or coverage) detected in the design.
These features are only supported in Questasim.
-- Compiling package axi_vip_pkg
** Warning: /opt/Xilinx/Vivado/2018.1/data/xilinx_vip/hdl/axi_vip_pkg.sv(4405): (vlog-2254) SystemVerilog testbench feature
(randomization or coverage) detected in the design.
These features are only supported in Questasim.
-- Compiling package axi4stream_vip_if_sv_unit
-- Importing package axi4stream_vip_pkg
-- Importing package xil_common_vip_pkg
-- Compiling interface axi4stream_vip_if
-- Compiling package axi_vip_if_sv_unit
-- Importing package axi_vip_pkg
-- Importing package xil_common_vip_pkg
-- Compiling interface axi_vip_if
-- Compiling interface clk_vip_if
-- Compiling interface rst_vip_if

Top level modules:
--none--
End time: 17:25:22 on Jun 07,2019, Elapsed time: 0:00:03
Errors: 0, Warnings: 3
Model Technology ModelSim DE vcom 10.6b Compiler 2017.05 May 25 2017
Start time: 17:25:22 on Jun 07,2019
vcom -32 -93 -work xil_defaultlib ../../../../UniversalAmpVivadoBlock.srcs/sources_1/ip/xadc_wiz_0/xadc_wiz_0.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity xadc_wiz_0
-- Compiling architecture xilinx of xadc_wiz_0
End time: 17:25:24 on Jun 07,2019, Elapsed time: 0:00:02
Errors: 0, Warnings: 0
Model Technology ModelSim DE vlog 10.6b Compiler 2017.05 May 25 2017
Start time: 17:25:24 on Jun 07,2019
vlog -32 -work xil_defaultlib "+incdir+../../../../UniversalAmpVivadoBlock.srcs/sources_1/bd/UniversalAmpBlock/ipshared/ec67/hdl" "+incdir+../../../../UniversalAmpVivadoBlock.srcs/sources_1/bd/UniversalAmpBlock/ipshared/02c8/hdl/verilog" "+incdir+../../../../UniversalAmpVivadoBlock.srcs/sources_1/bd/UniversalAmpBlock/ipshared/b193/hdl" "+incdir+/opt/Xilinx/Vivado/2018.1/data/xilinx_vip/include" ../../../../UniversalAmpVivadoBlock.ip_user_files/bd/UniversalAmpBlock/ip/UniversalAmpBlock_processing_system7_0_0/sim/UniversalAmpBlock_processing_system7_0_0.v
-- Compiling module UniversalAmpBlock_processing_system7_0_0

Top level modules:
UniversalAmpBlock_processing_system7_0_0
End time: 17:25:24 on Jun 07,2019, Elapsed time: 0:00:00
Errors: 0, Warnings: 0
Model Technology ModelSim DE vcom 10.6b Compiler 2017.05 May 25 2017
Start time: 17:25:24 on Jun 07,2019
vcom -32 -93 -work xil_defaultlib ../../../../UniversalAmpVivadoBlock.ip_user_files/bd/UniversalAmpBlock/sim/UniversalAmpBlock.vhd ../../../../UniversalAmpVivadoBlock.ip_user_files/bd/UniversalAmpBlock/ip/UniversalAmpBlock_axi_intc_0_0/sim/UniversalAmpBlock_axi_intc_0_0.vhd ../../../../UniversalAmpVivadoBlock.ip_user_files/bd/UniversalAmpBlock/ip/UniversalAmpBlock_rst_ps7_zynq_50M_0/sim/UniversalAmpBlock_rst_ps7_zynq_50M_0.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity UniversalAmpBlock
-- Compiling architecture STRUCTURE of UniversalAmpBlock
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Loading package ATTRIBUTES
-- Loading package std_logic_misc
-- Loading package ipif_pkg
-- Loading entity axi_lite_ipif
-- Loading package MATH_REAL
-- Loading entity intc_core
-- Loading entity axi_intc
-- Compiling entity UniversalAmpBlock_axi_intc_0_0
-- Compiling architecture UniversalAmpBlock_axi_intc_0_0_arch of UniversalAmpBlock_axi_intc_0_0
-- Loading entity proc_sys_reset
-- Compiling entity UniversalAmpBlock_rst_ps7_zynq_50M_0
-- Compiling architecture UniversalAmpBlock_rst_ps7_zynq_50M_0_arch of UniversalAmpBlock_rst_ps7_zynq_50M_0
End time: 17:25:26 on Jun 07,2019, Elapsed time: 0:00:02
Errors: 0, Warnings: 0
Model Technology ModelSim DE vlog 10.6b Compiler 2017.05 May 25 2017
Start time: 17:25:26 on Jun 07,2019
vlog -32 -work xil_defaultlib "+incdir+../../../../UniversalAmpVivadoBlock.srcs/sources_1/bd/UniversalAmpBlock/ipshared/ec67/hdl" "+incdir+../../../../UniversalAmpVivadoBlock.srcs/sources_1/bd/UniversalAmpBlock/ipshared/02c8/hdl/verilog" "+incdir+../../../../UniversalAmpVivadoBlock.srcs/sources_1/bd/UniversalAmpBlock/ipshared/b193/hdl" "+incdir+/opt/Xilinx/Vivado/2018.1/data/xilinx_vip/include" ../../../../UniversalAmpVivadoBlock.ip_user_files/bd/UniversalAmpBlock/ip/UniversalAmpBlock_auto_pc_0/sim/UniversalAmpBlock_auto_pc_0.v
-- Compiling module UniversalAmpBlock_auto_pc_0

Top level modules:
UniversalAmpBlock_auto_pc_0
End time: 17:25:27 on Jun 07,2019, Elapsed time: 0:00:01
Errors: 0, Warnings: 0
Model Technology ModelSim DE vcom 10.6b Compiler 2017.05 May 25 2017
Start time: 17:25:27 on Jun 07,2019
vcom -32 -93 -work xil_defaultlib ../../../../UniversalAmpVivadoBlock.srcs/sources_1/bd/UniversalAmpBlock/hdl/UniversalAmpBlock_wrapper.vhd ../../../../UniversalAmpVivadoBlock.srcs/sources_1/new/UniversalAmplifier.vhd ../../../../UniversalAmpVivadoBlock.srcs/sim_1/new/UniversalAmplifier_tb.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity UniversalAmpBlock_wrapper
-- Compiling architecture STRUCTURE of UniversalAmpBlock_wrapper
-- Compiling entity UniversalAmplifier
-- Compiling architecture Behavioral of UniversalAmplifier
-- Compiling entity UniversalAmplifier_tb
-- Compiling architecture Behavioral of UniversalAmplifier_tb
-- Loading entity UniversalAmplifier
End time: 17:25:28 on Jun 07,2019, Elapsed time: 0:00:01
Errors: 0, Warnings: 0
Model Technology ModelSim DE vlog 10.6b Compiler 2017.05 May 25 2017
Start time: 17:25:28 on Jun 07,2019
vlog -work xil_defaultlib glbl.v
-- Compiling module glbl

Top level modules:
glbl
End time: 17:25:29 on Jun 07,2019, Elapsed time: 0:00:01
Errors: 0, Warnings: 0
run_program: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 6580.855 ; gain = 0.000 ; free physical = 8859 ; free virtual = 22576
INFO: [USF-ModelSim-69] 'compile' step finished in '11' seconds
INFO: [USF-ModelSim-4] ModelSim::Simulate design
INFO: [USF-ModelSim-69] Executing 'SIMULATE' step in '/media/sf_bmd_repo/Cintel_master/ScannerGen2/UniversalAmp/UniversalAmpVivadoBlock/UniversalAmpVivadoBlock.sim/sim_1/behav/modelsim'
Program launched (PID=8626)
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 6580.855 ; gain = 0.000 ; free physical = 8807 ; free virtual = 22524

 

0 Kudos
6 Replies
Anonymous
Not applicable
398 Views

Re: Vivado 2018.1 Linux 64 bit Modelsim DE 32 bit - GUI not launching after simulation

Update: If I navigate to the .sim/../behav/modelsim directory nested under my Vivado project, there is a "simulate.sh", where if I run it, opens a modelsim embedded GUI whereby I'm able to see the errors Modelsim is encountering, which I presume is what might be holding this up from happening automatically. Just trying to work through those for now and see if this improves.

Anonymous
Not applicable
391 Views

Re: Vivado 2018.1 Linux 64 bit Modelsim DE 32 bit - GUI not launching after simulation

Ok, so I think it's because my PS7 system (via "Create HDL Wrapper") was my top level instance and that doesn't seem supported yet. Commenting that out, and now the "simulate.sh" opens and correctly simulates in Modelsim, however the question now remains, why doesn't Vivado run this script after completion so the modelsim GUI opens to view the simulation (and/or embed it inside Vivado window)? 

Am I missing something and Vivado is only running Modelsim behind the scenes to generate the simulation data but is not meant to open the actual Modelsim GUI automatically?

0 Kudos
Moderator
Moderator
373 Views
Registered: ‎04-24-2013

Re: Vivado 2018.1 Linux 64 bit Modelsim DE 32 bit - GUI not launching after simulation

Hi @Anonymous ,

In older versions of Vivado there was an option to by default only create the scripts and to not run the GUI. 

This was controlled by the -scripts_only option and could either be set via the tcl console or in the more options of SImulation Settings.

This was deprecated in later versions of the tools and was replaced with the export_simulation command.

If you have upgraded the project from a previous version or have this option set via a tcl script then it may be getting set as part of your project.

Best Regards
Aidan

 

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------
0 Kudos
Anonymous
Not applicable
360 Views

Re: Vivado 2018.1 Linux 64 bit Modelsim DE 32 bit - GUI not launching after simulation

Thanks for the reply,

I don't think it's that, because I just tried a "File/Export/Simulation" and it creates a pretty similar structure to what I've been seeing, except now there is a .sh script of my project name, which I still have to run (and it can't find UNISIM libs now either, so will just stick to "Run Simulation" for now). 

Would still be appreciated if anybody knows how to make the GUI automatically load to save me having to run the shell script everytime to look at the simulation.

 

0 Kudos
Moderator
Moderator
339 Views
Registered: ‎04-24-2013

Re: Vivado 2018.1 Linux 64 bit Modelsim DE 32 bit - GUI not launching after simulation

Hi @Anonymous ,

I think that you have misunderstood what I was saying.

I wasn't suggesting that you use the export_simulation command as this creates scripts and does not launch the simulator GUI.

I meant that you might have the -scripts_only option set for the launch_simulation command which gets called when you click on Run SImulaton in the Vivado GUI.

Can you look in the the Simualtion settings to see if you have any settings modified?

Capture.PNG

You could also try running launch_simulation from the tcl console to see if this changes the behaviour.

If you launch Vivado SImulator from the GUI, does it start as expected or only create the scripts?

From the log file details that you provided, it would appear that you are using ModelSIm 10.6b, this isn't a supported version of the tools to use with the 2018.1 version of Vivado. Version 10.6c is the minimum supported version as per UG973

UG973.PNG

If you are using IP with an earlier version of ModelSim, then this will cause issues both compiling the libraries and running the simulation.

Best Regards
Aidan

 

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------
0 Kudos
Anonymous
Not applicable
334 Views

Re: Vivado 2018.1 Linux 64 bit Modelsim DE 32 bit - GUI not launching after simulation

Hi Aidan,

if I run the generated "simulate.sh" output, Modelsim opens and the simulations is good. It's purely an oddity that the GUI never runs after successful completion.

"Run Simulation" find vlog etc.. and the final TCL output is this (which implies it's trying to launch, just nothing ever happens):

Errors: 0, Warnings: 0
run_program: Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 8148.367 ; gain = 0.000 ; free physical = 7689 ; free virtual = 21552
INFO: [USF-ModelSim-69] 'compile' step finished in '12' seconds
INFO: [USF-ModelSim-4] ModelSim::Simulate design
INFO: [USF-ModelSim-69] Executing 'SIMULATE' step in '/media/sf_bmd_repo/Cintel_master/ScannerGen2/UniversalAmp/UniversalAmpVivadoBlock/UniversalAmpVivadoBlock.sim/sim_1/behav/modelsim'
Program launched (PID=16919)
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:19 . Memory (MB): peak = 8148.367 ; gain = 0.000 ; free physical = 7516 ; free virtual = 21380

 

If I run "launch_simulation" providing the command path of my modelsim installation, it's the same outcome as if "Run Simulation", it compiles the simulation and then ends with the above output at the end, which 'claims' to have launched it with a PID but ends a few seconds later with no GUI running. Is there anywhere I can dig up the actual command that is 'launched' during any of this? 

I am running VIvado 2018.1 with a 32 bit modelsim DE, I feel like it might be related to Linux runtime as the above output log indicates the correct directory wherein "./simulate.sh" exists, which if I run on my own runs fine.

Thanks