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Observer app076
Observer
506 Views
Registered: ‎01-29-2014

Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

I have a strange version issue with simulating postroute netlist in Vivado. The same compilation script works in 2016.4 but not in 2018.3. How do I resolve this situation? I want to use 2018.3 because 2016.4/2017.4 do not support external signal naming in VHDL-2008 but now I am not even able to compile the files in 2018.3. Its so frustrating :(

 

I compile the Verilog netlist into a library and then use the library in my VHDL toplevel testbench.

My project files are:

vlog.prj: verilog GATE_LIB postroute.v

vhdl.prj: vhdl2008 xil_defaultlib ./tb.vhd

 

In tb.vhd, I have

LIBRARY GATE_LIB;

USE GATE_LIB.ALL;

DUT: ENTITY GATE_LIB.Top

 

The commands are:

xvlog -m64 --relax -prj vlog.prj

xvhdl --2008 --relax -L GATE_LIB -prj vhdl.prj

The last command fails with VRFC 10-2987 'top' is not compiled in library 'GATE_LIB' even though the xvlog command shows Top was analyzed into GATE_LIB.

 

 

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2 Replies
Observer app076
Observer
472 Views
Registered: ‎01-29-2014

Re: Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

My update:

I put in a component declaration for the Verilog module Top and replaced the USE entity.GATE_LIB.Top from the VHDL instantiation with just DUT:Top and now it works in 2018.3.

It seems strange that 2016.4 works with the entity instantiation type.

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Observer tdittrich
Observer
369 Views
Registered: ‎08-13-2014

Re: Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

Hi,

i have the same strange behavior and could fix it with the additional component declaration. Come on Xilinx Support it's still in Vivado 2019.1. ... I'm so tired of all the pitfalls i step into ...

 

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