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Registered: ‎01-26-2017

Vivado 2019.2 simulation not working with VHDL generic parameters at top-level

    We have Vivado projects in 2018.2, that we would like to migrate to Vivado 2019.2, but we're facing issues with passing VHDL generic parameters for simulation testbenches via the 'set_property generic' command.
    We're using XSIM mixed-mode simulation, with designs that have a majority of VHDL blocks, and a few Verilog sub-blocks.
    The top-level is a VHDL entity, with no ports, and a list of generic parameters.
    The simulation fails right after the xelab call every time we launch these simulations with Vivado 2019.2, whereas the same simulation works in Vivado 2018.2.
    The IPs have all been migrated, and synthesis works correctly (with similar way of setting the generic parameters).
    The xelab command that fails in Vivado 2019.2 is the following (with anonymized project name):
          xelab -wto 23660c591fa942ee815916266a1286eb --incr --debug typical --rangecheck --relax --mt 8 -generic_top AXIL_MASTER_PATTERN_FILE_G=/work/develop/repo/prj/sim/tc_003/pattern/axil_bfm_file.pat -generic_top CHECK_EVT_FORMAT_G=2 -generic_top CHECK_PATTERN_FILE_G=/work/develop/repo/prj/sim/tc_003/pattern/checker_file.pat -generic_top SYSTEM_ID_G=31 -generic_top SYSTEM_MAJOR_REV_NB_G=170 -generic_top SYSTEM_MINOR_REV_NB_G=187 -generic_top SYSTEM_MICRO_REV_NB_G=204 -generic_top USE_AUX_IF_G=true -L xil_defaultlib -L fifo_generator_v13_2_5 -L blk_mem_gen_v8_4_4 -L dist_mem_gen_v8_0_13 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_2 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L mipi_csi2_rx_ctrl_v1_0_8 -L high_speed_selectio_wiz_v3_5_2 -L mipi_dphy_v4_1_5 -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_6 -L zynq_ultra_ps_e_vip_v1_0_6 -L xlconstant_v1_1_6 -L lib_pkg_v1_0_2 -L lib_fifo_v1_0_14 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_22 -L axi_sg_v4_1_13 -L axi_dma_v7_1_21 -L xlconcat_v2_1_3 -L generic_baseblocks_v2_1_0 -L axi_data_fifo_v2_1_19 -L axi_register_slice_v2_1_20 -L axi_protocol_converter_v2_1_20 -L gigantic_mux -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_6 -L axis_protocol_checker_v2_0_4 -L xlslice_v1_0_2 -L axi_crossbar_v2_1_21 -L axi_clock_converter_v2_1_19 -L axi_dwidth_converter_v2_1_20 -L axi_mmu_v2_1_18 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot prj_tb_behav xil_defaultlib.prj_tb xil_defaultlib.glbl -log elaborate.log
    The error message issued is the following:
          ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
    Any ideas on how to fix this issue are welcome.
Best regards,
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Registered: ‎07-16-2008

This is known issue will be fixed in 2020.1. For the time being, you can do following

  1. Remove the generic_top from command
  2. If setting some different value through generic_top, use that value explicit in design
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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