Vivado 2019.2 simulation not working with VHDL generic parameters at top-level
We have Vivado projects in 2018.2, that we would like to migrate to Vivado 2019.2, but we're facing issues with passing VHDL generic parameters for simulation testbenches via the 'set_property generic' command.
We're using XSIM mixed-mode simulation, with designs that have a majority of VHDL blocks, and a few Verilog sub-blocks.
The top-level is a VHDL entity, with no ports, and a list of generic parameters.
The simulation fails right after the xelab call every time we launch these simulations with Vivado 2019.2, whereas the same simulation works in Vivado 2018.2.
The IPs have all been migrated, and synthesis works correctly (with similar way of setting the generic parameters).
The xelab command that fails in Vivado 2019.2 is the following (with anonymized project name):