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802 Views
Registered: ‎11-26-2014

Vivado VHDL simulator (2017.3) does not correctly handle "process(all)" sensitivity list.

Hi,

 

Vivado (2017.3) VHDL simulator (file set to 2008 mode) does not handle "process(all)" sensitivity list where the sensed signal is a a slice from inside a record.

 

- XILINX, can you confirm this?

- XILINX, when can I expect it to be fixed?

- XILINX, do you not have extensive test cases (other than the community doing it on behalf on you) to find these kinds of misses?

 

On below, the signal d(10) should change at 1 µs and 2 µs. But it does not.

 

    process(all)
    begin
        d(10) <= s_rec.a(1); -- This does not work in Vivado 2017.3 simulator !!!! Works with Aldec.
    end process;

 

Br, -Topi

 

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity test_process is
end;

architecture Behavioral of test_process is
    type rec is record
        a: std_logic_vector(15 downto 0);
        b: std_logic;
    end record;
    
    signal s_rec: rec;
    signal a: std_logic;
    signal b: std_logic;
    signal d: std_logic_vector(150 downto 0);
    
    signal x: std_logic_vector(15 downto 0);
    signal y: std_logic_vector(150 downto 0);
begin
    process(all)
    begin
        a <= s_rec.a(10);
    end process;
    
    process(all)
    begin
        d(10) <= s_rec.a(1); -- This does not work in Vivado 2017.3 simulator !!!! Works with Aldec.
    end process;
    
    process(all)
    begin
        y(3) <= x(15); -- This works ok.
    end process;

    process(all)
    begin
        b <= s_rec.b; -- This works ok.
    end process;

    process
    begin
        wait for 1.5 us;
        x <= (others => '1');
        wait;
    end process;
    
    process
    begin
        wait for 1 us;
        s_rec.a <= (others => '1');
        wait for 1 us;
        s_rec.a <= (others => '0');
        s_rec.b <= '1';
        wait;
    end process;
end;

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5 Replies
Moderator
Moderator
773 Views
Registered: ‎04-24-2013

Re: Vivado VHDL simulator (2017.3) does not correctly handle "process(all)" sensitivity list.

HI @topi-procemex,

 

Thanks for the sample code, I tried running it in Vivado Simulator from 2017.3, 2018.1 and in ModelSim 10.6c.

 

In ModelSim, you can see that there is a transition of the data shown after 1us, but the value on the bus has not changed.

 

ModelSIm.JPG

 

In Vivado 2017.3 this transition is not shown as the values have not changed.

 

Xsim_2017_3.JPG

 

Likewise for 2018.1

 

Xsim.JPG

 

What are you trying to see that you believe is incorrect?

 

Best Regards
Aidan

 

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751 Views
Registered: ‎11-26-2014

Re: Vivado VHDL simulator (2017.3) does not correctly handle "process(all)" sensitivity list.

Aidan,

 

This is the result from Aldec Active-HDL. I do not have Mentor so I cannot test with it.

 

You should notice that the bus d shows a transition like event at 1 µs, but looking at d(10), you notice it is actually a change of value rather than a mere glitch.

 

From your Mentor screenshot I cannot say wether Mentor is doing it the right way, or failing it.

 

simu_cap_1.jpg

 

Br, -Topi

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Moderator
Moderator
742 Views
Registered: ‎04-24-2013

Re: Vivado VHDL simulator (2017.3) does not correctly handle "process(all)" sensitivity list.

Hi @topi-procemex,

 

Thanks for the clarification, I can see the difference in behaviour now.

 

ModelSim has the same behaviour as your Aldec output and Vivado Xsim is not showing the expected change on d(10).

I will check if this has been reported previously and if not I will create a Change Request to get this issue fixed.

 

I will post back here with an update either way once I receive a response

 

Best Regards
Aidan

 

P.S. If you include the @ version of the persons name in your reply then they get notified.

It may help if you need a quick response in the future.

 

 

 

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Moderator
Moderator
732 Views
Registered: ‎04-24-2013

Re: Vivado VHDL simulator (2017.3) does not correctly handle "process(all)" sensitivity list.

Hi @topi-procemex,

 

I have created a Change Request to get this issue fixed.

 

Best Regards
Aidan

 

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Observer chamch
Observer
147 Views
Registered: ‎05-22-2017

Re: Vivado VHDL simulator (2017.3) does not correctly handle "process(all)" sensitivity list.

Not yet fixed in 2019.1

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