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Visitor haver
Visitor
2,264 Views
Registered: ‎02-12-2018

Vivado cannot find data file for my System Verilog simulation

I tried to load some data from a data file using a very simple system verilog testbench. Unfortunately

$fopen() returns -20000 and I could not find out why it could not find the data file, which I tried to include

in the simulation resources of my project, even letting it copy it into the project itself.

 

I tried to use $ferror() to see what might be wrong, but it appears as if Vivado does not support that at

this point in time (what a pity). What does the return code from $fopen() is supposed to mean?

What is the search path for data files the simulator usually takes? Is there a way to see this or even to

change, such that files are found?

 

I also tried to write a file, which actually worked. The imported data file is in the same directory, but seems

not to be found. I also simulated the very same test-bench on https://www.edaplayground.com which executed

my little example.

 

Testcode looks as follows:

 

    file = $fopen("I_AM_HERE.TXT", "w");
    $fclose(file);
    
    file = $fopen("nvme_data.data", "r");
    if (file <= 0) begin
       // errno = $ferror(file, errstr); Seems not to be supported by Xilinx tools!
       $display("err: Cannot open data file (rc=%0h/%d)!", file, file);
    end else begin
       while (!$feof(file)) begin
      rc = $fscanf(file, "%s %s %s %s\n", s[0], s[1], s[2], s[3]);
      for (i = 0; i < 4; i++) begin
             h[i] = s[i].atohex();
      end
      hex = { h[0], h[1], h[2], h[3] };
      $display("%s %s %s %s => %0h", s[0], s[1], s[2], s[3], hex);
       end
       $fclose(file);

 

Output is as follows:

...

READ: addr: 0000000f data: 1234567812345678123456780000000f
err: Cannot open data file (rc=ffffb1e0/     -20000)!
$finish called at time : 72 ns : File "/afs/vlsilab.boeblingen.ibm.com/proj/fpga/framework/haver/systemverilog/nvme_testbench.sv" Line 91
INFO: [USF-XSim-96] XSim completed. Design snapshot 'test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 10686.551 ; gain = 0.000 ; free physical = 172592 ; free virtual = 300000

 

Thanks for helping.

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18 Replies
Moderator
Moderator
2,228 Views
Registered: ‎04-24-2013

Re: Vivado cannot find data file for my System Verilog simulation

Hi @haver,

 

Have you tried adding the file as a source to the Simulation sources using Add Sources, Add or create simulation sources?

 

One other thing to check is the working directory, you can do this using the pwd command in the tcl console.

 

Often you might believe that you are working in one directory but are actually in another. This can change depending on how you start Vivado.

Best Regards
Aidan

 

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Visitor haver
Visitor
2,222 Views
Registered: ‎02-12-2018

Re: Vivado cannot find data file for my System Verilog simulation

Hi Aidan,

 

yes, I have tried to add the data resource and even copying it into the project itself, with no success so far.

I also added a "tryout" $fopen() trying to write a file and that worked somehow. The data file is in the same

directory, so I really wondered why that was not working.

 

Let me try your hint with checking the path in the tcl console tomorrow. Thanks for looking at my problem.

 

Regards

 

Frank

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Moderator
Moderator
2,213 Views
Registered: ‎11-09-2015

Re: Vivado cannot find data file for my System Verilog simulation

Hi @haver,

 

You might want to try to put your data file in "project.sim\sim_1\behav". It is usually working for me.

 

Hope that helps,

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor haver
Visitor
2,209 Views
Registered: ‎02-12-2018

Re: Vivado cannot find data file for my System Verilog simulation

bash-4.1$ find -name "*.data"
./systemverilog_example.ip_user_files/mem_init_files/nvme_data.data
./systemverilog_example.sim/sim_1/behav/nvme_data.data
./systemverilog_example.srcs/sim_1/imports/systemverilog/nvme_data.data

 

Somehow it already ended up in that directory (Linux). I did a pwd in the tcl window and it said I am in a directory where the datafile was also present. So I already have a bunch of those in my directory tree, but it still refuses finding it for opening.

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Visitor haver
Visitor
2,207 Views
Registered: ‎02-12-2018

Re: Vivado cannot find data file for my System Verilog simulation

exec ls -ls nvme_data.data
1 -rw------- 1 haver gloadl 576 Feb 9 11:25 nvme_data.data
pwd
/<mydirectoryies>/systemverilog

The tcl shell seems to be in the directory from where I started the vivado tool. So outside the project, but I have a copy of my little nvme_data.data file there too. Access rights should be fine too, as far as I can judge. I can read/write the file nicely from the console.
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Moderator
Moderator
2,202 Views
Registered: ‎11-09-2015

Re: Vivado cannot find data file for my System Verilog simulation

Hi @haver,

 

If it is a binary file, you might want to use:

file = $fopen("nvme_data.data", "rb");


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor haver
Visitor
2,196 Views
Registered: ‎02-12-2018

Re: Vivado cannot find data file for my System Verilog simulation

Actually it is a text file with some hexadecimal numbers. Maybe it would be better on the long run to have it binary, but I wanted to try it out first.

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Visitor eyosiasy
Visitor
1,232 Views
Registered: ‎11-06-2018

Re: Vivado cannot find data file for my System Verilog simulation

Is there any update on this thread? Please let me know if you have found a solution. I am dealing with a similar symptom.

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Contributor
Contributor
645 Views
Registered: ‎10-01-2013

Re: Vivado cannot find data file for my System Verilog simulation

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Visitor haver
Visitor
623 Views
Registered: ‎02-12-2018

Re: Vivado cannot find data file for my System Verilog simulation

Hi,

I think I ended up in using $readmemh() and $writememh() to get the data in and out of my simulation. But even that was not troublefree.

/* Circumvention for simulator problems we have seen. Xilinx change request was filed */       
`ifdef SIM_XSIM
                static logic [7:0] fname[128]; /* works only for xsim */
`else
                static string fname; /* works for ncsim but not for xsim */
`endif
                $sformat(fname, "SNAP_LBA_%h.bin", lba_addr);
                $readmemh(fname, axi_data);
 
The problem with string versus logic array is not there if one uses $writememh(). I wanted to have a special filename depending on the data I write/read (LBA - logical block address).
 
Regards
 
Frank
 
 
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Contributor
Contributor
609 Views
Registered: ‎10-01-2013

Re: Vivado cannot find data file for my System Verilog simulation

Thanks for that, Frank. 

I was considering something like that myself: converting all the binary test data to ASCII, breaking it up into smaller files and naming each one with an index, then loading them in sequence in the testbench.  Doable, but a bit of a headache.

Any comment from the Xilinx team?  Is this a known bug?  Is there a workaround to get fopen() to succeed?

 

 

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Adventurer
Adventurer
593 Views
Registered: ‎01-27-2008

Re: Vivado cannot find data file for my System Verilog simulation

Hi,

As Vivado simulation likes to make obscure run directories, I tend to use absolute paths in my stimulus files. 

That works around Vivado's idiosyncracies.

I also use purely binary stimulus for more compact storage. 

Here's what I developed as, essentially, a template for every testbench I have...

   parameter ROOT_SIM = "/home/local/some/fixed/path/to/stimulus/";

   parameter MAXINFILE_SIZE = 300001;  
   logic [31:0]     data [MAXINFILE_SIZE];  

   int fid;
   int code;
   string 	       gauss_fn;
   initial begin
      gauss_fn = "/scripts/matlab/binary.dat";

      // file is continuous 32b int samples
// Note @bkuschak I simply append the fixed ROOT_PATH to a specific filepath - usually at the top of my project-specific directory structure fid = $fopen( {ROOT_SIM, gauss_fn}, "rb"); code = $fread(data, fid); $display("end reading stimulus file %s %d\n. Location after read: %2d", gauss_fn, fid, $ftell(fid)); $fclose(fid); end

Then all the data is in an array (data).

Works around Vivado's problems every time.

Best,

Jerry

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Contributor
Contributor
586 Views
Registered: ‎10-01-2013

Re: Vivado cannot find data file for my System Verilog simulation

Thank you for the advice, Jerry.  

I tried absolute paths, using both forward and backward slashes. (This is a windows machine).  I have also used very short paths to avoid problems with Windows path length limitations.   None of these solutions worked unfortunately.  It's very clearly seeing my file.  If I remove the file from the simulation behav directory I get an fopen() return code of 0.  With the file there I get a code of -20000, which is later rejected by fread().

For your situation, I agree, using absolute paths can be handy, especially if another tool generates new stimulus files externally.  Otherwise, have you tried adding the stimulus file to your simulation project as either an 'Unknown File type' or as a 'Memory Initialization File'?  That will cause Vivado to copy it to the runtime directory before running the sim so you can use a relative path in the fopen.

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Adventurer
Adventurer
575 Views
Registered: ‎01-27-2008

Re: Vivado cannot find data file for my System Verilog simulation

So the -20000 isn't rejected in my case. I haven't added the files to the simulation set as I haven't needed to using the abs path method.

I just tried my tb, you can see the -20000 corresponding to fid (referencing above snip). It certainly worked - also I do a $ftell after to know it read 'so many' values from whatever file I used...

0 ns:  window_generic_tb   starting...
end reading stimulus file /scripts/matlab/some.dat      -20000
. Location after read: 1200004
Where the "end reading" line is generated from this line of code:     
$display("end reading stimulus file %s %d\n. Location after read: %2d", gauss_fn, fid, $ftell(fid));

 I'm sorry this didn't help, but you can see that I get -20000 as well.

So -20000 breaks down into 0xFFFF_B1E0. That's not consistent with the definition (going by 1364-2001) which is supposed to be bit31 set followed by a small number, but I wouldn't call it incorrect. I get that and read the data into an array, then access the array.

Not sure what's wrong given your -20000 which is the same thing I get (although after $fread).

Posting a code snip might help....

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Contributor
Contributor
567 Views
Registered: ‎10-01-2013

Re: Vivado cannot find data file for my System Verilog simulation

Please refer to my link earlier in the thread.  I posted a new thread with the details before I had found this thread, and later updated my post with a link to this one.  It has a code snippet and the error code from the TCL console from fread().  For whatever reason my fread() doesn't like the -20000.  It seems to interpret it as -1.

I'm using Verilog and 'integer', while you are using SV and 'int' but I don't expect that to be a problem.

I can try playing around with fseek() / ftell() and see if they complain about the fp.

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Adventurer
Adventurer
564 Views
Registered: ‎01-27-2008

Re: Vivado cannot find data file for my System Verilog simulation

@bkuschak 

Thanks for pointing that link out... just read through the thread.

Can you actually post the watered down testbench with the binary file and just the initial process.

Looks ok to me at a glance. I'll give it a shot, albiet in Ubuntu (and primarily 2018.2).

 

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Contributor
Contributor
557 Views
Registered: ‎10-01-2013

Re: Vivado cannot find data file for my System Verilog simulation

Problem solved.  I feel a bit stupid about this, but I simply had the wrong order to the parameters in fread().  It should be 

    ret = $fread(rxd, fp);

not

    ret = $fread(fp, rxd);

Too bad the simulator doesn't have better type checking to raise a warning about this..  One is an integer the other a reg [63:0]. 

Thanks for your help.  Looking at your snippet more closely I was able to spot my error.

 

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Adventurer
Adventurer
551 Views
Registered: ‎01-27-2008

Re: Vivado cannot find data file for my System Verilog simulation

Yep makes sense. often the small things.

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