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Visitor willlindo
Visitor
17,012 Views
Registered: ‎11-09-2014

Vivado: error while trying to simulate with user defined data type

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I'm having a problem to simulate on Vivado the same project that works fine on Xilinx ISE. The following error happens when I want to execute a behavioral simulation:

 

[VRFC 10-619] entity port mem_vdata_in does not match with type vectordata_type of component port ["C:/Users/Will/Desktop/wilian_proj/opensimdrisc_project/project_Vivado/project_Vivado.srcs/sources_1/imports/opensimdrisc_project/tb_cpu.vhd":58]

 

[VRFC 10-619] entity port mem_vdata_out does not match with type vectordata_type of component port ["C:/Users/Will/Desktop/wilian_proj/opensimdrisc_project/project_Vivado/project_Vivado.srcs/sources_1/imports/opensimdrisc_project/tb_cpu.vhd":59]

 

The error refers to a data type specified as:

 

type vectordata_type is array (k-1 downto 0) of std_logic_vector(31 downto 0);

 

which is a port from a component being used on my test bench  file. Here is part of it:

 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

use STD.textio.all;
use ieee.std_logic_textio.all;

use work.cfg.all;
use work.datatypes.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_cpu IS
END tb_cpu;

ARCHITECTURE behavior OF tb_cpu IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT cpu
port(
clk: in std_logic;
reset: in std_logic;
dbg_halted: out std_logic;
dbg_load_ir: out std_logic; -- I added
mem_data_in: in std_logic_vector(31 downto 0);
mem_data_out: out std_logic_vector(31 downto 0);
mem_vdata_in: in vectordata_type;
mem_vdata_out: out vectordata_type;
mem_address: out std_logic_vector(31 downto 0);
mem_access: out std_logic_vector(2 downto 0);
mem_ready: in std_logic
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal mem_data_in : std_logic_vector(31 downto 0) := (others => '0');
signal mem_vdata_in : vectordata_type;
signal mem_ready : std_logic := '0';

--Outputs
signal dbg_halted : std_logic;
signal mem_data_out : std_logic_vector(31 downto 0);
signal mem_vdata_out : vectordata_type;
signal mem_address : std_logic_vector(31 downto 0);
signal mem_access : std_logic_vector(2 downto 0);

-- Clock period definitions
constant clk_period : time := 20 ns;

--------------------------------------------------------------------
file datain, instructions: text;

constant wordSize: integer := 32;
signal instInput : std_logic_vector( (wordSize-1) downto 0) := "00000000000000000000000000000000";
signal sig_ready: std_logic := '1';
signal load_ir: std_logic;
signal resetOnce : std_logic := '0';
signal vData : vectordata_type;
signal counter, instCounter, rep: integer := 0;
constant repetitions: integer := 448; -- 128 Points FFT
-------------------------------------------------------------------

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: cpu PORT MAP (
clk => clk,
reset => reset,
dbg_halted => dbg_halted,
dbg_load_ir => load_ir,
mem_data_in => mem_data_in,
mem_data_out => mem_data_out,
mem_vdata_in => mem_vdata_in,
mem_vdata_out => mem_vdata_out,
mem_address => mem_address,
mem_access => mem_access,
mem_ready => mem_ready
);

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
28,958 Views
Registered: ‎09-13-2014

Re: Vivado: error while trying to simulate with user defined data type

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Thanks for confirming that it's working for behavioral simulation. 

 

Regarding post-synth or post-imp, it's expected and the reasons are

 

1> Entity cpu contains complex port(vectordata_type) and after synthesis, complex ports are bit-blasted to so that you have normal port in form of scalar or vector.

2> In post-synth or post-imp, your test bench is same but netlist has different ports due to bit-blasting and hence ERROR.

 

Solution

 

Any DUT should not have complex port. Port should be only scalar or vector else same kind of issue will be see for post-synth or post-imp so to make it work with same test bench, you need to create a wrapper over CPU. The wrapper will such that it will have simple scalar/vector port and use that wrapper as  DUT and with that you should not see any issue at any kind of simulation.

 

Please let us know if you need any help in creating wrapper.

 

--dhiRAj

 

10 Replies
Xilinx Employee
Xilinx Employee
16,997 Views
Registered: ‎09-13-2014

Re: Vivado: error while trying to simulate with user defined data type

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From ERROR message, it seems that issue is coming becuase the port type on component( which is vectordata_type) is not the same as that declared on entity CPU. You may like to double check that.

 

Can you please change the component instantiation to entity instantiation and see how the tool is behaving. If it's still showing ERROR it means there is issue in port type mismatch. If it pass then likely issue on tool and for that would request you to share the test case.

 

Solution: Change component instance to entity instance and can be done by changing 

 

from 'uut: cpu PORT MAP ('

to 'uut: entity work.cpu PORT MAP (' --> assuming that the cpu entity is being dumped in same library as that of  tb_cpu.

 

--dhiRAj

 

Visitor willlindo
Visitor
16,983 Views
Registered: ‎11-09-2014

Re: Vivado: error while trying to simulate with user defined data type

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Thanks for replying dprasad,

 

The sugestion you've made worked like a charm for behavioral simulation, but when I tried to run both post-synthesis and post-implementation functional simulation the error happened again:

 

ERROR: [VRFC 10-719] formal port/generic <mem_vdata_in> is not declared in <cpu> [../../../../project_Vivado.srcs/sources_1/imports/opensimdrisc_project/tb_cpu.vhd:105]
ERROR: [VRFC 10-704] formal \mem_vdata_in[1]\ has no actual or default value [../../../../project_Vivado.srcs/sources_1/imports/opensimdrisc_project/tb_cpu.vhd:98]
ERROR: [VRFC 10-1504] unit behavior ignored due to previous errors [../../../../project_Vivado.srcs/sources_1/imports/opensimdrisc_project/tb_cpu.vhd:44]

 

Here is the cpu entity declaration:

 

entity cpu is
port(
clk: in std_logic;
reset: in std_logic;
dbg_halted: out std_logic;
dbg_load_ir: out std_logic; -- I added
mem_data_in: in std_logic_vector(31 downto 0);
mem_data_out: out std_logic_vector(31 downto 0);
mem_vdata_in: in vectordata_type;
mem_vdata_out: out vectordata_type;
mem_address: out std_logic_vector(31 downto 0);
mem_access: out std_logic_vector(2 downto 0);
mem_ready: in std_logic
);
end cpu;

 

and here is the updated test bench file:

 

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

use STD.textio.all;

use ieee.std_logic_textio.all;

 

use work.cfg.all;

use work.datatypes.all;

 

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

 

ENTITY tb_cpu IS

END tb_cpu;

 

ARCHITECTURE behavior OF tb_cpu IS

 

-- Component Declaration for the Unit Under Test (UUT)

 

COMPONENT cpu

port(

clk: in std_logic;

reset: in std_logic;

dbg_halted: out std_logic;

dbg_load_ir: out std_logic; -- I added

mem_data_in: in std_logic_vector(31 downto 0);

mem_data_out: out std_logic_vector(31 downto 0);

mem_vdata_in: in vectordata_type;

mem_vdata_out: out vectordata_type;

mem_address: out std_logic_vector(31 downto 0);

mem_access: out std_logic_vector(2 downto 0);

mem_ready: in std_logic

);

END COMPONENT;

 

 

--Inputs

signal clk : std_logic := '0';

signal reset : std_logic := '0';

signal mem_data_in : std_logic_vector(31 downto 0) := (others => '0');

signal mem_vdata_in : vectordata_type := (others => (others => '0'));

signal mem_ready : std_logic := '0';

 

--Outputs

signal dbg_halted : std_logic;

signal mem_data_out : std_logic_vector(31 downto 0);

signal mem_vdata_out : vectordata_type := (others => (others => '0'));

signal mem_address : std_logic_vector(31 downto 0);

signal mem_access : std_logic_vector(2 downto 0);

 

-- Clock period definitions

constant clk_period : time := 20 ns;

 

--------------------------------------------------------------------

file datain, instructions: text;

 

constant wordSize: integer := 32;

signal instInput : std_logic_vector( (wordSize-1) downto 0) := "00000000000000000000000000000000";

signal sig_ready: std_logic := '1';

signal load_ir: std_logic;

signal resetOnce : std_logic := '0';

signal vData &colon; vectordata_type;

signal counter, instCounter, rep: integer := 0;

constant repetitions: integer := 448; -- 128 Points FFT

-------------------------------------------------------------------

 

BEGIN

 

-- Instantiate the Unit Under Test (UUT)

uut: entity work.cpu PORT MAP (

clk => clk,

reset => reset,

dbg_halted => dbg_halted,

dbg_load_ir => load_ir,

mem_data_in => mem_data_in,

mem_data_out => mem_data_out,

mem_vdata_in => mem_vdata_in,

mem_vdata_out => mem_vdata_out,

mem_address => mem_address,

mem_access => mem_access,

mem_ready => mem_ready

);

 

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Xilinx Employee
Xilinx Employee
28,959 Views
Registered: ‎09-13-2014

Re: Vivado: error while trying to simulate with user defined data type

Jump to solution

Thanks for confirming that it's working for behavioral simulation. 

 

Regarding post-synth or post-imp, it's expected and the reasons are

 

1> Entity cpu contains complex port(vectordata_type) and after synthesis, complex ports are bit-blasted to so that you have normal port in form of scalar or vector.

2> In post-synth or post-imp, your test bench is same but netlist has different ports due to bit-blasting and hence ERROR.

 

Solution

 

Any DUT should not have complex port. Port should be only scalar or vector else same kind of issue will be see for post-synth or post-imp so to make it work with same test bench, you need to create a wrapper over CPU. The wrapper will such that it will have simple scalar/vector port and use that wrapper as  DUT and with that you should not see any issue at any kind of simulation.

 

Please let us know if you need any help in creating wrapper.

 

--dhiRAj

 

Visitor willlindo
Visitor
16,949 Views
Registered: ‎11-09-2014

Re: Vivado: error while trying to simulate with user defined data type

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Thanks for replying again dprasad,

 

I created a new file called cpu_wraper.vhd where i only use std_logic and std_logic_vector data types for its ports. The only place where I use vectordata_type is in the instantiation of cpu.vhd as a component inside cpu_wrapper:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use work.cfg.all;
use work.datatypes.all;

 

entity cpu_wrapper is
port(
clk : IN std_logic;
reset : IN std_logic;
dbg_halted : OUT std_logic;
dbg_load_ir : OUT std_logic;
mem_data_in : IN std_logic_vector(31 downto 0);
mem_data_out : OUT std_logic_vector(31 downto 0);
mem_vdata_in_0 : IN std_logic_vector(31 downto 0);
mem_vdata_in_1 : IN std_logic_vector(31 downto 0);
mem_vdata_out_0 : OUT std_logic_vector(31 downto 0);
mem_vdata_out_1 : OUT std_logic_vector(31 downto 0);
mem_address : OUT std_logic_vector(31 downto 0);
mem_access : OUT std_logic_vector(2 downto 0);
mem_ready : IN std_logic
);
end cpu_wrapper;

architecture arch of cpu_wrapper is

COMPONENT cpu
port(
clk : IN std_logic;
reset : IN std_logic;
dbg_halted : OUT std_logic;
dbg_load_ir : OUT std_logic; -- I added
mem_data_in : IN std_logic_vector(31 downto 0);
mem_data_out : OUT std_logic_vector(31 downto 0);
mem_vdata_in : IN vectordata_type;
mem_vdata_out : OUT vectordata_type;
mem_address : OUT std_logic_vector(31 downto 0);
mem_access : OUT std_logic_vector(2 downto 0);
mem_ready : IN std_logic
);
END COMPONENT;

--Inputs
signal mem_vdata_in : vectordata_type;

--Outputs
signal mem_vdata_out : vectordata_type;

begin

wrappedCpu: entity work.cpu PORT MAP (
clk => clk,
reset => reset,
dbg_halted => dbg_halted,
dbg_load_ir => dbg_load_ir,
mem_data_in => mem_data_in,
mem_data_out => mem_data_out,
mem_vdata_in => mem_vdata_in,
mem_vdata_out => mem_vdata_out,
mem_address => mem_address,
mem_access => mem_access,
mem_ready => mem_ready
);

--Inputs
mem_vdata_in(0) <= mem_vdata_in_0;
mem_vdata_in(1) <= mem_vdata_in_1;

--Outputs
mem_vdata_out_0 <= mem_vdata_out(0);
mem_vdata_out_1 <= mem_vdata_out(1);

end arch;

 

 

The test bench was only modified to include cpu_wrapper.

 

But an error, now on cpu_wrapper.vhd, still happens when I try to run synthesis:

 

[Synth 8-2032] formal mem_vdata_in is not declared ["project_Vivado.srcs/sources_1/imports/opensimdrisc_project_Switch_Op/cpu_wrapper.vhd":86]

 

and also the behavioral simulation gives the same error as before:

 

[VRFC 10-718] formal port <mem_vdata_in> does not exist in entity <cpu>. Please compare the definition of block <cpu> to its component declaration and its instantion to detect the mismatch. ["project_Vivado/project_Vivado.srcs/sources_1/imports/opensimdrisc_project_Switch_Op/cpu_wrapper.vhd":63]

 

 

I tried to run simulation and synthesis using both "wrappedCpu: entity work.cpu PORT MAP (" and "wrappedCpu: cpu PORT MAP (", but none worked.

 

Again, when I simulate on Xilinx ISE everything works. If any other information is required, please let me know.

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Xilinx Employee
Xilinx Employee
16,942 Views
Registered: ‎09-13-2014

Re: Vivado: error while trying to simulate with user defined data type

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Can you please share your complete project so that I can look at it in detail suggest/do whatever fix is required. 

 

--dhiRAj

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Visitor willlindo
Visitor
16,933 Views
Registered: ‎11-09-2014

Re: Vivado: error while trying to simulate with user defined data type

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Here are the sources

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Xilinx Employee
Xilinx Employee
16,919 Views
Registered: ‎09-13-2014

Re: Vivado: error while trying to simulate with user defined data type

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I looked at design shared by you. There is a typo in cpu.vhd, by mistake you have commented the port declaration 'mem_vdata_in' and 'mem_vdata_out' present at line no. 31 and 32. Please uncomment those and it should work as behavioral level.

 

For post-synth or post-imp, please make sure that cpu_wrapper is top module for synthesis not 'cpu' and with that it should work file.

 

let me know if you are seeing seeing issue.

 

--dhiRAj

 

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Visitor willlindo
Visitor
16,900 Views
Registered: ‎11-09-2014

Re: Vivado: error while trying to simulate with user defined data type

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Ohh my bad, I changed the cpu.vhd file on Xilinx ISE sources  and forgot about updating the one in Vivado sources.

 

Now the implementation is working and I can run all simulations, but I'm stil having problems with them.

 

The problem is with a signal created with enumeration, it is being initialized as a high impedance value (Z) and never changes state. But I also implemented the design without using the components with "vectordata_type" and I havent had this problem.

 

So I don't know if this problem was generated by the modifications I did in order to make Vivado accept my design or if it is just another bug.

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Visitor willlindo
Visitor
16,891 Views
Registered: ‎11-09-2014

Re: Vivado: error while trying to simulate with user defined data type

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For some reason when the enumeration went to "halt" state it would never leave, so all I did was change to another state and now is working

Thanks for all the help
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Xilinx Employee
Xilinx Employee
8,410 Views
Registered: ‎10-24-2013

Re: Vivado: error while trying to simulate with user defined data type

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Hi,
Please close the thread my marking the solution in the interest of other users.
Thanks,Vijay
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