Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎06-12-2018

Vivado hangs when compiling unisim simprim libraries

Hello everyone,

I'm using Vivado 2020.1 with Modelsim 20.1 in Ubuntu 18.04.

I'm trying to compile the unisim and simprim libraries through Vivado using the following:

compile_simlib -simulator modelsim -simulator_exec_path {/home/pstr/intelFPGA/20.1/modelsim_ase/bin} -family all -language all -library all -dir {/home/pstr/Projects/GRLIB} -force -verbose


Vivado runs for a few minutes and then hangs. I have waited for more than an hour. I'm also including the output of Vivado.


INFO: [setup_ip_static_library-Tcl-23] Data extracted from repository. Inspected 586 IP libraries.

> Current directory :- '/home/pstr'
> Library data paths:- '/home/pstr/tools/Xilinx/Vivado/2020.1/data'
> Device family(s) :- 'versal, virtexuplus58g, virtexuplus, kintexuplus, zynquplus, zynquplusrfsoc, kintexu, virtexu, virtex7, virtex7l, qvirtex7, qvirtex7l, spartan7, artix7, artix7l, qartix7, qartix7l, kintex7, kintex7l, qkintex7, qkintex7l, zynq, azynq, qzynq'
> Library(s) :- 'simprim, unisim'
> Language(s) :- 'vhdl, verilog'
> Compilation mode :- '64-bit'
INFO: [Vivado 12-5496] Finding simulator executables and checking version...

> executing '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vcom -version -64'...
output file: '.cxl.modelsim.version'
> forking '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vcom -version -64'
return code: '0'
Time taken: 0 mins (0 secs)
WARNING: [Vivado 12-5495] Detected incompatible modelsim simulator installation version '2020.1'! The supported simulator version for the current Vivado release is '2019.4'.
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...

Compiling libraries for 'modelsim' simulator in '/home/pstr/Projects/GRLIB'

> executing '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vlib /home/pstr/Projects/GRLIB/secureip'...
> forking '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vlib /home/pstr/Projects/GRLIB/secureip'
return code: '0'
Time taken: 0 mins (0 secs)

> executing '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vmap secureip /home/pstr/Projects/GRLIB/secureip'...
output file: '/home/pstr/Projects/GRLIB/secureip/.cxl.verilog.secureip.secureip.lin64.log'
> forking '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vmap secureip /home/pstr/Projects/GRLIB/secureip'
return code: '0'
Time taken: 0 mins (0 secs)

Compiling verilog library 'secureip'...
> executing '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vlog -source -64 -work secureip -f /home/pstr/Projects/GRLIB/secureip/.cxl.verilog.secureip.secureip.lin64.cmf'...
output file: '/home/pstr/Projects/GRLIB/secureip/.cxl.verilog.secureip.secureip.lin64.log'
> forking '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vlog -source -64 -work secureip -f /home/pstr/Projects/GRLIB/secureip/.cxl.verilog.secureip.secureip.lin64.cmf'
return code: '0'
Time taken: 2 mins (116 secs)

> executing '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vlog -source -64 -sv -svinputport=relaxed -suppress vlog-2583 -work secureip -f /home/pstr/Projects/GRLIB/secureip/.cxl.systemverilog.secureip.secureip.lin64.cmf'...
output file: '/home/pstr/Projects/GRLIB/secureip/.cxl.verilog.secureip.secureip.lin64.log'
> forking '/home/pstr/intelFPGA/20.1/modelsim_ase/bin/vlog -source -64 -sv -svinputport=relaxed -suppress vlog-2583 -work secureip -f /home/pstr/Projects/GRLIB/secureip/.cxl.systemverilog.secureip.secureip.lin64.cmf'


Any insights will be appreciated.

Tags (3)
0 Kudos
1 Reply
Registered: ‎07-16-2008

It looks you're targetting Modelsim specific edition for Intel? I don't think it's officially supported.

Please refer to UG973 v2020.1 for the compatible 3rd party tools for Vivado 2020.1.

Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
0 Kudos