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pedro_uno
Advisor
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Registered: ‎02-12-2013

Vivado simulation load time is very long for FIR filter cores

Hello Guys,

 

I am trying to simulate a block that contains an FIR Compile 7.2 core.  Reload time for the simulation is very long, about 10 minutes.  I find that if I comment out the FIR core the simulation reloads in a few seconds. I am using  Vivado simulator version 2016.4.

 

What kind of thing could cause these impractically long simulator load times?

 

Thanks,

 

   Pete

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DSP in hardware and software
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thakurr
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Registered: ‎09-15-2016

Hi @pedro_uno

 

Please check similar issue in the below thread.Hope it helps.

https://forums.xilinx.com/t5/Simulation-and-Verification/Simulation-is-Very-Slow-why/td-p/662970

 

Regards

Rohit

 

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Regards
Rohit
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pedro_uno
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Registered: ‎02-12-2013

Yes, I saw that one but it looks ISE specific. I am using the Vivado simulator.

 

Still, the same idea may apply so I looked through all the tabs on the FIR Compiler GUI.  I found nothing about simulation model, structural versus behavioral.  In my simulation project settings I found this and switched it to "Blackbox model".  That has not reduced load time.

 

sim_setting.png

 

Any other ideas?  I really cannot debug my design with these load times.

 

    Pete

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DSP in hardware and software
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pedro_uno
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Registered: ‎02-12-2013

This is the pop up that runs 10 or 15 minutes at simulation (re)load time.

 

Screenshot from 2017-03-10 09-46-54.png

 

I also get a huge number of these messages when the FIR core is included in the simulation.

WARNING: [VRFC 10-516] comparison between unequal length arrays always returns FALSE [/wrk/2016.4/nightly/2016_12_14_1733598/packages/customer/vivado/data/ip/xilinx/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd:1957]

 

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DSP in hardware and software
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pedro_uno
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Hello Guys,

I still have no relief on this. It is very hard to work with this core when I cannot simulate.

 

If anyone can take a look I attach a zipped up project.  Under ./sim there is a setup.tcl file that sets up the simulation. I would be curious to know if you can load the simulation in a finite amount of time in Vivado 2016.4.

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DSP in hardware and software
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mistercoffee
Scholar
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Registered: ‎04-04-2014

I concur this is a nightmare. Has this been fixed in 2017.2 or is there a fix yet?

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tsjorgensen
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Registered: ‎09-13-2011

Still a problem in 2017.2. Doing som interpolation and decimation with about 120 DSP elements takes 20 minutes to start simulation on new i7-core machine with 32GB RAM.

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s002wjhw
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Registered: ‎06-26-2015

I have same issue its ridiculous long time. using 2017.2 anyone got it working faster?
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mistercoffee
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Registered: ‎04-04-2014


@s002wjhw wrote:
I have same issue its ridiculous long time. using 2017.2 anyone got it working faster?

My only solution right now is to either disable the FIR cores (if that particular sim is not testing them) or switch o the incremental compile option. This obviously only helps after the first fir but it did seem to speed things up.

 

Either was it's stupid that such a bug got reported (in more than one thread) and didn't get fixed in the next update. 

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s002wjhw
Voyager
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Registered: ‎06-26-2015

could you tell me where is the option for incremental compile option? if nothing work I guess I have to download a free version of ACtive-hdl or modelsim.
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mistercoffee
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Registered: ‎04-04-2014

It's under settings -> simulation -> compilation

 

tick the box for xsim.compile.incremental. It's the 6th option down the list

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pedro_uno
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Registered: ‎02-12-2013

I just retried this in Vivado 2017.2. The problem has not been solved. Simulation (re)load is about 15 minutes on a pretty good Win7 machine.

 

I think the simulator is resynthesizing the entire FIR core at load time, yikes.

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DSP in hardware and software
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josephsamson
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Registered: ‎10-05-2010

I have the same problem of long simulation elaboration times with the FIR filters. I tried the incremental compile setting, but it didn't help.

 

---

Joe Samson

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mistercoffee
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Registered: ‎04-04-2014

Can anyone say whether this issue has been fixed on 2017.3/4? This really is a big deal. Simulations are taking so long now when a FIR is involved. If this hasn't been fixed it needs doing asap.

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tsjorgensen
Explorer
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Registered: ‎09-13-2011

This is still a problem in 2018.3. Isn't there anything Xilinx can do about this? Please!

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mistercoffee
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Registered: ‎04-04-2014

That this is still an issue is unforgiveable. Proof in itself that Xilinx does not give a flying **** about it's simulator. Bug ridden mess.

johnribe
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Registered: ‎06-07-2018

I have the same problem in Vivado 18.2

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ryanjohnson8
Explorer
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Registered: ‎05-30-2017

I have the same problem in Vivado 2019.2. It is massively slowing down my development time. Xilinx, please have mercy on us and fix this issue.

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mistercoffee
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Registered: ‎04-04-2014

@thakurr you are the only Xilinx employee to respond to this thread so I'm tagging you. This bug has been in Vivado sim for over 3 years. It makes a huge difference to our ability to run sims. We know that you guys aren't interested in furthering your simulator capabilities but this isn't really acceptable. It's a bug fix,if you put someone on it I'm sure it can be resolved relatively quickly, after all it didn't used to be an issue.

Is someone going to look at fixing it?  Anyone?

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ezhhen
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Registered: ‎10-18-2019

THE PROBLEM STILL EXISTS!

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joehoward2
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Registered: ‎05-23-2018

Please fix this

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ekigwana
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Registered: ‎07-15-2015

For any one else irritated by this,

I have found that if I synthesize just the fir cores, the simulation goes from taking tens of minutes to start up to less than a minute.

Edit: Starting with a project with no simulation products:

  1. Run synthesis (once)
  2. Run Simulation
  3. Make adjustments to design as required
  4. Return to Step 2 as required

If you run simulation first, synthesis will not help.

steve_farmer
Adventurer
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Registered: ‎06-25-2014

Can you explain a little more about what you mean when you say 'synthesize just the fir cores'. Are they not included OOC anyway and so pre-synthesized?

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mistercoffee
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Registered: ‎04-04-2014

It's been so long since I could be bothered to simulated a FIR core.. but I'm pretty sure I always had them synthesized OOC when I ran a sim? Or is this again release version dependent. What version of Vivado are you using @ekigwana ?

steve_farmer
Adventurer
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Registered: ‎06-25-2014

I'm interested in this because I'm pretty sure it relates to a post I've just created...

https://forums.xilinx.com/t5/Simulation-and-Verification/Long-simulation-times-when-using-XFFT-IP-XSIM-2019-2/td-p/1186806 

My DUT is my own custom IP (which has a xfft IP simular to the FIR IP in it) that I've previously created in another project and add/instantiate it to the simulation project by adding it's IP generation location to the IP Catalog.

When I run the simulation xelab takes the vast majority of the time (4 out of the total time of 5 mins), even though the only difference when I run simulation is that my scripts change a testbench test number via the --generic_top switch to xelab. Without the XFFT IP total time is less than 1 min.

In the elaborate.log it takes the 4 mins to go from this step...

    Pass Through NonSizing Optimizer

...to this step...

    Completed static elaboration

    INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

....is there was some way of locking the IP (or the whole DUT) from being re-elaborated I'm sure this would speed things up?

mistercoffee
Scholar
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Registered: ‎04-04-2014

Does the incremental compile option help you? I'm sure I tried this years ago with the FIR to no avail but you can try it.

 

mistercoffee_0-1608208418561.png

 

steve_farmer
Adventurer
Adventurer
587 Views
Registered: ‎06-25-2014

Great idea. Unfortunately I believe I am already doing that for both compile and elaborate.....

xvlog --incr --relax -L axi_vip_v1_1_6 -L axi4stream_vip_v1_1_6 -L xilinx_vip -prj testbench_top_vlog.prj 2>&1 | tee compile.log

xvhdl --incr --relax -prj testbench_top_vhdl.prj 2>&1 | tee -a compile.log

xelab -wto 073e1cba47e54ffdbc10374d5158b3df --incr --debug typical --relax --mt 8 -L xilinx_vip -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L c_reg_fd_v12_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_pipe_v3_0_6 -L xbip_dsp48_addsub_v3_0_6 -L xbip_addsub_v3_0_6 -L c_addsub_v12_0_14 -L c_mux_bit_v12_0_6 -L c_shift_ram_v12_0_14 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_16 -L cmpy_v6_0_18 -L floating_point_v7_0_17 -L xfft_v9_1_3 -L axis_infrastructure_v1_1_0 -L axis_register_slice_v1_1_20 -L axis_dwidth_converter_v1_1_19 -L xil_defaultlib -L axi4stream_vip_v1_1_6 -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_6 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_top_behav xil_defaultlib.testbench_top xil_defaultlib.glbl -log elaborate.log -sv_lib dpi

ekigwana
Observer
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Registered: ‎07-15-2015

Vivado v2018.2 (64-bit)

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