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Newbie
Newbie
390 Views
Registered: ‎10-20-2020

Vivado synthesis timing simulation

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Hello.
There are some things I don't understand about synthesis timing simulation in vivado.

When you do synthesis timing simulation in vivado, how do you measure the time from where to where?
For example, does it include input/output delays, or does it include component delays?

I'd be happy to know.

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-12-2020

Hi @imo,

Post-Synthesis timing simulation uses the estimated timing delay from the device models and does not include interconnect delay.

Post-Implementation timing simulation uses actual timing delays.

 
Thanks,
R.Samhoud
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-12-2020

Hi @imo ,

Please refer to UG900:https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug900-vivado-logic-simulation.pdf page 67 for a detailed description of running simulation.

 

Please let me know if you still need more assistance.
Thanks,
R.Samhoud
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Newbie
Newbie
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Registered: ‎10-20-2020

Thanks for the answer.
I have one question after browsing the site.
The TIP on page 68 says that the interconnect delay is not included in the TIP. However, on the same page Post-Synthesis Timing Simulation says that estimated values for component delay are available. I am aware that interconnect delay is included in component delay in a larger sense.
Is interconnect delay included in Post-Synthesis Timing Simulation?
Thank you for your help.

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Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎02-12-2020

Hi @imo,

Post-Synthesis timing simulation uses the estimated timing delay from the device models and does not include interconnect delay.

Post-Implementation timing simulation uses actual timing delays.

 
Thanks,
R.Samhoud
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Newbie
Newbie
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Registered: ‎10-20-2020

Thank you.
Thanks to you, I was able to understand it.