UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer grimlk
Observer
3,741 Views
Registered: ‎02-06-2017

Vivado15.2)Floating point in verilog

Jump to solution
 
 
 
 
Hello Guys.
 
 
I built a module that takes inputs and performs divide operations and then compares the sizes.
 
 
module test(output reg out1 , input in1, input in2);
 
parameter k=10'd1000;
parameter j=10'd800;
real devide1;
real devide2;
assign devide1=in1/k;
assign devide2=in2/j;
 
always @(posedge in1 or in2) begin
if(devide1>=devide2) begin
out1<=1'b0;
end
 
else begin
out1<=1'b1;
end
end
 
endmodule
 
but i met this error
 
concurrent assigntment to a non-net devide1 is not permitted
concurrent assigntment to a non-net devide2 is not permitted
 
I spent a lot of time looking for a solution but I could not find the cause.
I need your help.
Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Instructor
Instructor
6,574 Views
Registered: ‎08-14-2007

Re: Vivado15.2)Floating point in verilog

Jump to solution

As already pointed out, your code cannot be synthesized.  However if you're just using it for simulation, the error comes from the declarations for "devide1" and "devide2":

 

real devide1;
real devide2;
 
A real is similar to a reg.  That means is should be assigned in a process, not in a continuous assignment like a wire.
 
You could change your assignments from:
 
assign devide1=in1/k;
assign devide2=in2/j;
 
to:
 
always @*
  begin
    devide1=in1/k;
    devide2=in2/j;
  end
 
Then you should be able to simulate it.
-- Gabor
0 Kudos
2 Replies
Teacher muzaffer
Teacher
3,735 Views
Registered: ‎03-31-2012

Re: Vivado15.2)Floating point in verilog

Jump to solution

@grimlk floating point is not synthesizable in verilog. You can use fixed-point operations instead. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Instructor
Instructor
6,575 Views
Registered: ‎08-14-2007

Re: Vivado15.2)Floating point in verilog

Jump to solution

As already pointed out, your code cannot be synthesized.  However if you're just using it for simulation, the error comes from the declarations for "devide1" and "devide2":

 

real devide1;
real devide2;
 
A real is similar to a reg.  That means is should be assigned in a process, not in a continuous assignment like a wire.
 
You could change your assignments from:
 
assign devide1=in1/k;
assign devide2=in2/j;
 
to:
 
always @*
  begin
    devide1=in1/k;
    devide2=in2/j;
  end
 
Then you should be able to simulate it.
-- Gabor
0 Kudos