cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
639 Views
Registered: ‎05-10-2019

Wait for internal signal?

Jump to solution

I would like tow ait on an internal ready signal in my test bench.

So like this

wait on sys_test.DFT_READY until sys_test.DFT_READY='1';

where sys_test is the instance name of the UUT and DFT_READY is the relevant signal. However, when I put this line in trhe code it says "Illegal selected name prefix". What am I doing wrong?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
599 Views
Registered: ‎08-01-2012

Are you set to VHDL 2008? external names are not available previously.

Can you post the whole code?

View solution in original post

5 Replies
Highlighted
Scholar
Scholar
610 Views
Registered: ‎08-01-2012

First of all, in your example, wait on is not needed, you can simply use wait until.

This is because you are trying to do an external name verilog style, not VHDL style.

In VHDL, external names are referenced using <<>> and must include an entire signal declaration. So for your example, assuming DFT_READY is a std_logic, you would need:

wait until <<signal sys_test.DFT_READY : std_logic >> = '1';

Obviously this can little long winded, and cumbersum if you need the same signal in multiple places, so usually its best to use an alias:

alias a_DFT_READY is << signal sys_test.DFT_READY : std_logic >>;
...
wait until a_DFT_READT = '1';

Caveat here is that sys_test must be visible, ie. the alias is declared after the sys_test instantiation.

Highlighted
Visitor
Visitor
605 Views
Registered: ‎05-10-2019

Alias doesn't work. It says

[HDL 9-806] Syntax error near "<". 

I put it in the stimuli process before "begin".

0 Kudos
Highlighted
Scholar
Scholar
600 Views
Registered: ‎08-01-2012

Are you set to VHDL 2008? external names are not available previously.

Can you post the whole code?

View solution in original post

Highlighted
Visitor
Visitor
564 Views
Registered: ‎05-10-2019

Yes that is the reason, although this thread tells that VHDL 2008 is switched on permanntly since 2016.x and I have 2018.3

0 Kudos
Highlighted
Scholar
Scholar
559 Views
Registered: ‎08-01-2012

@luzhandr 

Its been available to use, but the user still has to specify 2008 for each file . 2002 is the default mode when reading VHDL

0 Kudos